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Circuit Operating Descriptions
13-6 Video
13-6-1 Outline
ZIC1(A/V decoder with video encoder) diverges from the 27MHz crystal, then generates VSYNC and HSYNC.
ZIC1(A/V decoder with video encoder) does RGB encoding, copy guard processing and D/A conversion of 8bit
video data internally inputted from video decoder block by ZIC1.
Video signal converted into analog signal is outputted via amplifier of analog part.
A/V Decoder
Vaddis 7 With
Video Encoder
ZIC1
13-6-2 NTSC/PAL Digital Encoder (VADDIS 7 ; Built in video encode)
ZIC1 inputted from pin 161 with 27MHz generates HSYNC and VSYNC which are based on video signal.
ZIC1 is synchronous signals with decoded video signal and control the output timing of 8bit video signal.
The separate signal is encoded to NTSC by control of ZIC1.
The above signals, which are CVBS (Composite Video Burst Synchronized)/G (GREEN)/Y,
Y (S_VIDEO)/R (RED)/Pr and C (S_VIDEO)/B (BLUE)/Pb [PIN162], are selectively outputted CVBS +S_VIDEO,
RGB/Component by the rear switch. In Course of encoding, 8bit data can extend to 10bit or more.
To convert the extended data to quantization noise as possible, ZIC1 adopts 10bit D/A converter.
ZIC1 perform video en-coding as well as copy protection.
13-6-3 Amplifier (VIC1: LA73054)
VIC1 is 6dB amplifier.
Based on CVBS signal, the final output level must be 2Vpp without 75ohm terminal resitance.
Because the level of video encoder output is only 1.1Vpp, the level is adjusted with the special amplifier.
When mute of pin 5 is high active, if the pin is floating and connecte to power, the output signal is never
ouputted.
CVBS, Y, C, R, Pb(B), Pr(R) outputted from video encoder are inputted to VIC1 (Pin 2, 8, 6, 16, 14).
The signal to which gain is adjusted by amplifier is outputted from jack via 75ohm Resistance (VR11~VR16).
13-14
Video data
CVBS
Y/R/V
C/B/U
CVBS/G/Y
Digital Video data
Fig. 13-17 Video Output Block Diagram
CVBS
Y
6dB
C
LOW
AMP
PASS
FILTER
75ohm
(6MHz)
Drive
Y
Pb
Pr
MM1623
ZR36721
CVBS
Y
C
Y
&
Pb
Pr
SCART
Jack
HDMI
Samsung Electronics
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