Marantz SA-11S2 Service Manual page 43

Q102 : XCF01S
1 20
D0
(DNC) 2 19
CLK 3 18
17
TDI 4
VO20/VOG20
5 16
TMS
Top View
6 15
TCK
CF 7 14
OE/RESET 8 13
(DNC) 9 12
CE 10 11
Boundary
Pin Name Scan Order
D0
CLK
OE/RESET
CE
CF
CEO
TMS
TCK
Boundary
Pin Name Scan Order
TDI
TDO
VCCINT
VCCO
VCCJ
GND
DNC
VCCJ
VCCO
VCCINT
TDO
(DNC)
(DNC)
CLK CE
(DNC)
CEO
(DNC)
GND
TCK
Control
TMS
and
JTAG
TDI
Interface
TDO
CF
Boundary
Scan Function
4 Data Out D0 is the DATA output pin to provide data for configuring an
FPGA in serial mode. The D0 output is set to a
3 Output Enable high-impedance state during ISPEN (when not clamped).
Configuration Clock Input. Each rising edge on the CLK input
0 Data In increments the internal address counter if the CLK input is
selected, CE is Low, and OE/RESET is High.
20 Data In Output Enable/Reset (Open-Drain I/O). When Low, this input
holds the address counter reset and the DATA output is in a
high-impedance state. This is a bidirectional open-drain pin
19 Data Out
that is held Low while the PROM is reset. Polarity is not
18 Output Enable programmable.
Chip Enable Input. When CE is High, the device is put into
low-power standby mode, the address counter is reset, and
15 Data In
the DATA pins are put in a high-impedance state.
Configuration Pulse (Open-Drain Output). Allows JTAG
22 Data Out
CONFIG instruction to initiate FPGA configuration without
powering down FPGA. This is an open-drain output that is
21 Output Enable
pulsed Low by the JTAG CONFIG command.
Chip Enable Output. Chip Enable Output (CEO) is connected
12 Data Out
to the CE input of the next PROM in the chain. This output is
Low when CE is Low and OE/RESET input is High, AND the
internal address counter has been incremented beyond its
Terminal Count (TC) value. CEO returns to High when
11 Output Enable
OE/RESET goes Low or CE goes High.
JTAG Mode Select Input. The state of TMS on the rising edge
of TCK determines the state transitions at the Test Access
Mode Select Port (TAP) controller. TMS has an internal 50KΩ resistive
pull-up to V
not driven.
JTAG Clock Input. This pin is the JTAG test clock. It
sequences the TAP controller and all the JTAG test and
Clock
programming electronics.
p (
Boundary
Scan Function
JTAG Serial Data Input. This pin is the serial input to all JTAG
instruction and data registers. TDI has an internal 50KΩ
Data In
resistive pull-up to V
the pin is not driven.
JTAG Serial Data Output. This pin is the serial output for all
JTAG instruction and data registers. TDO has an internal
Data Out
50KΩ resistive pull-up to V
system if the pin is not driven.
+3.3V Supply. Positive 3.3V supply voltage for internal logic.
+3.3V, 2.5V, or 1.8V I/O Supply. Positive 3.3V, 2.5V, or 1.8V
supply voltage connected to the output voltage drivers and
input buffers.
+3.3V, 2.5V, or 1.8V JTAG I/O Supply. Positive 3.3V, 2.5V, or
1.8V supply voltage connected to the TDO output voltage
driver and TCK, TMS, and TDI input buffers.
Ground
Do not connect. (These pins must be left unconnected.)
Data
Memory
Data
Address
Pin Description
to provide a logic "1" to the device if the pin is
CCJ
)
Pin Description
to provide a logic "1" to the device if
CCJ
to provide a logic "1" to the
CCJ
1-55
OE/RESET
CEO
Serial
Interface
DATA (D0)
Serial Mode
ds123_01_30603
20-pin TSSOP
(VO20/VOG20)
1
3
8
10
7
13
5
6
20-pin TSSOP
(VO20/VOG20)
4
17
18
19
20
11
2, 9, 12, 14, 15, 16