Truth Table - Onkyo DV-CP701 Service Manual

IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
Q1251: IC41LV16100-50T 16-MBIT DYNAMIC RAM
PIN CONFIGURATION
VCC
1 50
I/O0
2 49
1/O1
3 48
1/O2
4 47
1/O3
5 46
VCC
6 45
1/O4
7 44
1/O5
8 43
1/O6
9 42
1/O7
10 41
NC
11 40
NC 15 36
16 35
NC
17 34
WE
18 33
RAS
NC 19 32
NC 20 31
A0 21 30
22 29
A1
23 28
A2
A3 24 27
VCC 25 26
PIN DESCRIPTION
Address input
A0-A9
I/O0-15 Data inputs/outputs
Write enable
WE
Output enable
OE
Row address strobe
RAS
UCAS Upper column address strobe
Lower column address strobe
LCAS
Power
VCC
Ground
GND
No connection
NC

TRUTH TABLE

Function
Standby
Read: Word
Read: Lower Byte
Read: Upper Byte
Write: Word (Early Write)
Write: Lower Byte (Early Write)
Write: Upper Byte (Early Write)
Read Write
EDO Page-Mode Read
EDO Page-Mode Read
EDO Page-Mode
Read-Write
Hidden Refresh
RAS-Only Refresh
CBR Refresh
FUNCTIONAL BLOCK DIAGRAM
OE
GND
WE
1/O15
1/O14
CAS
LCAS
1/O13
CLOCK
1/O12
UCAS
GENERATOR
GND
1/O11
1/O10
1/O9
1/O8
RAS
RAS
NC
CLOCK
GENERATOR
NC
LCAS
UCAS
REFRESH
CE
COUNTER
A9
A8
A7
A6
A5
A4
GND
ADDRESS
BUFFERS
RAS
H
L
L
L
L
L
L
L
1st Cycle L
2nd Cycle L
Any Cycle L
1st Cycle L
2nd Cycle L
1st Cycle L
2nd Cycle L
1st Cycle L H L
2nd Cycle L H L
L
H L
WE
CONTROL
CAS
LOGICS
COLUMN DECODES
SENSE AMPLIFIERS
MEMORY ARRAY
LCAS UCAS WE OE
H H X
L L H
L H H
H L H
L L L
L H L
H L L
L L H L H L
H L H L H
H L H L H
L H L H H
H L H L L
H L H L L
H L H L H L
H L H L H L L H
L L H
L L L
H H X
L L X
OE
CONTROL
WE
LOGICS
DATA I/O BUS
1.048.576 x 16
Address t /t I/O
R C
X X High-Z
L ROW/COL Dout
L ROW/COL Lower Byte. Dout
Upper Byte, High-Z
L ROW/COL Lower Byte, High-Z
Upper Byte. Dout
X ROW/COL Din
X ROW/COL Lower Byte. Din
Upper Byte, High-Z
X ROW/COL Lower Byte, High-Z
Upper Byte. Din
ROW/COL Dout, Din
L ROW/COL Dout
L NA/COL Dout
L NA/NA Dout
X ROW/COL Din
X NA/COL Din
L ROW/COL Dout, Din
NA/COL Dout, Din
L ROW/COL Dout
X ROW/COL Dout
X ROW/NA High-Z
X X High-Z
DV-CP701
I/O0-I/O15