Marantz DV9500 Service Manual page 121

Mnemonic Input/Output
DGND G
AGND G
CLKIN_A I
CLKIN_B I
COMP1,2 O
DAC A O
DAC B O
DAC C O
DAC D O
DAC E O
DAC F O
P_HSYNC I
P_VSYNC I
P_BLANK I
S_BLANK I/O
S_HSYNC I/O
S_VSYNC I/O
Y9–Y0 I
C9–C0 I
S9–S0 I
RESET I
R I
SET1,2
SCLK I
SDA I/O
ALSB I
V P
DD_IO
V P
DD
V P
AA
V I/O
REF
EXT_LF I
RTC_SCR_TR I
2
I C I
GND_IO
PIN FUNCTION DESCRIPTIONS
Function
D igital Ground.
Analog Ground.
Pixel Clock Input for HD (74.25 MHz Only, PS Only (27 MHz), SD Only (27 MHz).
Pixel Clock Input. Requires a 27 MHz reference clock for progressive scan mode or a 74.25 MHz
(74.1758 MHz) reference clock in HDTV mode. This clock is only used in dual modes.
Compensation Pin for DACs. Connect 0.1 µF capacitor from COMP pin to V
CVBS/Green/Y/Y Analog Output.
Chroma/Blue/U/Pb Analog Output.
Luma/Red/V/Pr Analog Output.
In SD Only Mode: CVBS/Green/Y Analog Output; in HD Only Mode and Simultaneous HD/SD
Mode: Y/Green [HD] Analog Output.
In SD Only Mode: Luma/Blue/U Analog Output; in HD Only Mode and Simultaneous HD/SD
Mode: Pr/Red Analog Output.
In SD Only Mode: Chroma/Red/V Analog Output; in HD Only Mode and Simultaneous HD/SD
Mode: Pb/Blue [HD] Analog Output.
Video Horizontal Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.
V ideo Vertical Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode .
V ideo Blanking Control Signal for HD in Simultaneous SD/HD Mode and HD
Video Blanking Control Signal for SD Only.
Video Horizontal Sync Control Signal for SD Only.
Video Vertical Sync Control Signal for SD Only.
SD or Progressive Scan/HDTV Input Port for Y Data. Input port for interleaved progressive scan
data. The LSB is set up on Pin Y0. For 8-bit data input, LSB is set up on Y2.
Progressive Scan/HDTV Input Port 4:4:4 Input Mode. This port is used for the Cb[Blue/U] data.
The LSB is set up on pin C0. For 8-bit data input, LSB is set up on C2.
SD or Progressive Scan/HDTV Input Port for Cr[Red/V] data in 4:4:4 input mode. LSB is set up
on pin S0. For 8-bit data input, LSB is set up on S2.
This input resets the on-chip timing generator and sets the ADV7310/ADV7311 into default register
setting. RESET is an active low signal.
A 3040Ω resistor must be connected from this pin to AGND and is used to control the amplitudes
of the DAC outputs.
2
C Port Serial Interface Clock Input.
I
2
I C Port Serial Data Input/Output.
TTL Address Input. This signal sets up the LSB of the I
2
the I C filter is activated, which reduces noise on the I
Power Supply for Digital Inputs and Outputs.
Digital Power Supply.
Analog Power Supply.
Optional External Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
External Loop Filter for the Internal PLL.
M ultifunctional Input. Real time control (RTC) input, timing reset input, subcarrier reset input.
This input pin must be tied high (V
Digital Input/Output Ground.
2
2
C interface.
) for the ADV7310/ADV7311 to interface over the I
DD_IO
119
.
AA
Only Mode .
C address. When this pin is tied low,
2
C port.