More About Mode 0; More About Mode 1 - Intel MCS 51 User Manual

in~.
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
The baud rate generatormode is similar to the auto-re-
loadmcde, in that a rolloverin TH2 causesthe Timer 2
registerstObe reloadedwith the Id-bit vahsein registers
RCAP2Hand RCAP2L,which are preset by software.
Now, the baud rates in Modes 1 and 3 are determined
by Timer 2'soverflowrate as follows:
Timer 2
@clfiow Rate
Modes 1,3 BaudRate =
16
The Tim= can be configured for either "timer" or
"counter" operation.In the most typicalapplications, i t
is configuredfor "timer" operation(C/T2 = O)."Tim-
er" operationis a fittle different for Timer 2 when it's
being used as a baud rate generator. Normally, as a
timer it wouldincrement every machine cycle(thus at
Y,, the
mdlator
frequency). Asa
baud rate generator,
however,it incrementsevery state time (thus at ~, the
oscillatorfrequency). I n that case the baud rate is given
by the formula
Mcdes 1,3
OscillatorFrequency
'aud 'te = 32x [65536– (RCAP2H,RCAP2L)1
where (RCAP2H, RCAF2L) is the content of
RCAP2Hand RCAP2Ltaken as a Id-bit unsignedin-
teger.
Timer 2 as a baud rate generatoris shownin Figure 16.
This Figure is valid only if RCLK + TCLK = 1 in
T2CON.Note that a rolloverin TH2 doesnot set TP2,
and willnot generatean interrupt. Therefore,the Timer
2 interrupt doesnot have to be disabledwhenTimer 2
is in the baud rate generator mode. Note too, that if
EXEN2 is set, a l-to-O transition in T2EX will set
EXF2 but will not cause a reload from (RCAP2H,
RCAP2L)to (TH2,TL2). Thus whenTimer 2 is in use
as a baud rate generator,T2EX can be usedas an extra
external interrupt, if desired.
It shouldbe noted that when Timer 2 is running(TR2
= 1) in "timer" function in the baud rate generator
mod~ one shouldnot try to read or write TH2or TL2.
Under these conditionsthe Timer is beingincremented
everystate time, and the results of a read or write may
not be accurate.The RCAP rcgistm may be read, but
shouldn'tbe written to, becausea write mightoverlapa
reload and cause write and/or reload errors. Turn the
Timer off (clear TR2) before ruessing the Timer 2 or
RCAP registers,in this case.
MoreAboutModeO
Serial data
enters and exits through RXD. TXD out-
puts the shifl clock. 8 bits are tranarnitted/received:8
data bits (LSBfwst).The baud rate is fixedat !/,2 the
oscillatorfrequency.
Figure 17showsa simplifiedfunctioned diagramof the
serial port in ModeO,and associatedtiming.
Trsnamissionis initiated by any instruction that uses
SBUF as a destinationregister. The "write to SBUF'
signalat S6P2also loadsa 1into the 9th positionof the
transmit shift registerand tells the TX Controlblockto
commencea transmission.The internal timing is such
that one till machine cycle will elapse between"write
to SBUF," and activationof SEND.
SEND enables the output of the shift register to the
alternate output functionline of P3.0, and sdsoenables
SHIFf CLOCKto the alternate output functionline of
P3.1. SHIPT CLOCK is
low
during S3, S4, and S5 of
everymachinecycle,and high during S6,S1and S2.At
S6P2of everymachinecycle in which SEND is active,
the contents of the transmit shift register are shiftedto
the right one position.
As data bits shift out to the right, zeroescomein from
the left. Whenthe MSBof the data byte is at the output
positionof the shift register, then the 1that was initial-
Iy loaded into the 9th position,is just to the left of the
MSB,and all positionsto the left of that containzeroes
This condition flags the TX Control block to do one
last shitl and then deactivateSEND and set TL Bothof
these actions occur at SIP1 of the loth machinecycle
after "write to SBUF."
Receptionis initiated by the condition REN = 1 and
R1 = O.At S6P2of the next machine cyclq the RX
Control unit writes the bits 11111110to the receive
shift register,and in the next clock phaseactivatesRE-
CEIVE.
RECEIVE enables SHIFT CLOCK to the alterstate
output function line of P3.1. SHIIW
CLOCK makes
transitions
at S3P1and S6P1 of every machine cycle.
At S6P2of everymachinecycle in which RECEIVEis
active,the contentsof the receiveshift registerare shift-
ed to the left one position. The value that comes in
from the right is the vrduethat was sampledat the P3.O
pin at S5P2of the same machine cycle.
As &ta bits comein from the righL 1sshift out to the
left. When the Othat was initiallyloadedinto the right-
most positionarrivesat the leftmostpositionin the shift
register, it flags the RX Control block to do one last
shift and load SBUF. At SIP1 of the Klth machine
cycle after the write to SCON that cleared RI, RE-
CEIVE is cleared and RI is set.
MoreAboutMode 1
Ten bits are transmitted (through TXD), or received
(through RXD): a start bit (0), 8 data bits (LSBtirst),
and a stop bit (l). on receive, the stop bit gces into
RBg in SCON.In the 8051the baud rate is determined
by the Timer 1 overflowrate. In the 8052it is deter-
minedeither by the Timer 1overtlowratej or the Timer
2 overtlowrate or both (one for transmit and the other
for receive).
Figure 18showsa simplitlsdfunctionaldiagramof the
serial port in Mode 1, and associatedtimingsfor trsns-
mit
receive.
3-17