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Schematic Diagram
Main Board
MST9259V
VCPU
VCC12V_AUDIO
VCPU
VCC12V_AUDIO
+1.8V_VDD
+2.5MVDD
+3.3DVDD
+3.3AVDD
+2.5V_DMC
+2.5V_DMQ
+2.5MVDD
B2
B1
RIN
RIN
GNDR
GNDR
TXD
GIN
GIN
RXD
GNDG
GNDG
DDC_CLK
SOG
SOG
DDC_DAT
BIN
BIN
DDC_WP
GNDB
GNDB
ST_DET1
HSY NC
HSY NC
ST_DET2
VSYNC
VSY NC
DVI_CLK
R+
R+
DVI_DAT
R-
R-
G+
G+
G-
G-
B+
B+
HDCP_RST
B-
B-
CLK+
CLK+
CLK-
CLK-
3.INPUT
B3
ST_DET2
ST_DET1
DDC_WP
ALE
ALE
DDC_CLK
RD
RD
DDC_DAT
WR
WR
RXD
HWRESET
HWRESET
TXD
INT
INT
DVI_CLK
DVI_DAT
AD0
AD0
HDCP_RST
AD1
AD1
VCPU
AD2
AD2
onPANEL_5V/3.3V
AD3
AD3
onBACKLITE
AUDIO_SD
onPOWER
AUDIO_MU
6.MCU
B6
VCC12V_AUDIO
AUDIO_MU
AUDIO_SD
VOLUME
Volume
7.AUDIO
B4
onPOWER
AdjBACKLITE
AdjBACKLITE
onBACKLITE
onPanel_5V/3.3V
VCPU
VLCD
VCC12V_AUDIO
VLCD
+1.8V_VDD
+2.5MVDD
+3.3DVDD
+3.3AVDD
+2.5MVDD
+2.5V_DMQ
+2.5V_DMC
2.POWER
4.SCALER
SCHEMATIC
+3.3AVDD
VLCD
VLCD
+3.3AVDD
+3.3DVDD
+2.5MVDD
+1.8V_VDD
+2.5MVDD
FSDQM1
FSDQM0
FSDQSU3
FSDQSU2
FSDQSU1
FSDQSU0
FSDATAU[0..31]
FSDATAU[0..31]
/FSWE
/FSCAS
/FSRAS
FSBKSEL0
FSBKSEL1
FSCLK+
FSCLK-
FSCKE
FSDDR[0..11]
FSADDR[0..11]
44
+1.8V_VDD
+2.5MVDD
+3.3DVDD
+2.5MVDD
+2.5V_DMQ
+2.5V_DMC
B5
+2.5V_DMQ
FSDQM1
+2.5V_DMC
FSDQM0
FSDQSU3
FSDQSU2
FSDQSU1
FSDQSU0
FSDATAU[0..31]
/FSWE
/FSCAS
/FSRAS
FSBKSEL0
FSBKSEL1
FSCLK+
FSCLK-
FSCKE
FSADDR[0..11]
5.Frame Memory
Title
TOP
Size
Document Number
B
G1773-J-AC-X-1-070309
Date:
Friday , March 09, 2007
Sheet
2
Chapter 7
Rev
J
of
8
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