Sony CFD-S40CP Service Manual page 18

CFD-S40CP
IC1001 ES3880 MP3 DECOMPRESSION
Pin No. Pin name
1 VDD3
2 RAS#
3 DWE#
4 – 12 DA0 – 8
13 – 28 DBUS0 – 15
29 RESET#
30 VSS
31 VDD3
32 – 39 YUV0 – 7
40 VSYNC
41 HSYNC
42 CPUCLK
43 PCLK2X
44 PCLK
45 AUX0
46 AUX1
47 AUX2
48 AUX3
49 AUX4
50 VSS
51 VDD3
52 AUX6
53 AUX5
54 AUX7
55 – 62 LD0 – 7
63 LWR#
64 LOE#
65 LCS3
66 LCS1
67 LCS0
68 – 79 LA0 – 11
80 VSS
81 VPP
82 – 87 LA12 – 17
88 ACLK
89 AOUT/SEL-PLL0
90 ATCLK
91 ATFS/SEL-PLL1
92 DA9/DOE#
93 AIN
94 ARCLK
95 ARFS
96 TDMCLK
97 TDMDR
98 TDMFS
99 CAS#
100 VSS
18
I/O
— Power supply terminal
O Strobe signal for M11B41256A (DRAM) column address output (Active: L)
O Write enable signal output to M11B41256A (DRAM) (Active: L)
O Address bus output to M11B41256A (DRAM)
I/O Data bus terminal to/from M11B41256A (DRAM)
I System reset signal input
— Ground terminal
— Power supply terminal
O Not used (Open)
I/O Not used (Open)
I/O Not used (Open)
I System clock signal input from ES3889 (DSP)
I/O Clock for pixel double signal (27MHz)
I/O Clock for pixel signal (13.5MHz)
I GFS signal input from CXD3068Q
O FOK signal output
O CD serial data signal output
O CPU interface clock signal output to CXD3068Q
O I data request signal output
— Ground terminal
— Power supply terminal
O CD serial clock signal output
O System data strobe signal output
O CD serial chip select signal output
I/O Data bus to/from RISK interface
O Not used (Open)
O Output enable signal output to RISK interface
O Chip enable signal output to HT27C020 (ROM)
O Clock signal output to system data
O Clock signal output to CXD3068Q (DSP)
I/O Address bus to/from HT27C020 (ROM)
— Ground terminal
— Protection voltage terminal
I/O Address bus to/from HT27C020 (ROM)
I/O Master clock signal of audio DAC data
I/O Serial data to/from audio interface
O Transferring audio bit clock signal output
O Sync. signal output of transferring audio frame signal
O Output enable signal output to M11B41256A (DRAM)
I Serial data input from audio interface
I Bit clock signal input from audio receiver
I Frame sync. signal input from audio receiver
I Serial clock input from CXD3068Q
I Serial data input from CXD3068Q
I Frame sync. signal input from CXD3068Q
O Strobe signal for M11B41256A (DRAM) row address output (Active: L)
— Ground terminal
Description