Sony MCE-K700 Service Manual page 50

Pin No. Pin Name
57 PDCLK
58 V
SS
59 VSYNC
60 HSYNC
61 SO
62 FID
63 V
DD
64 XIICEN
I/O
13.5MHz pixel data clock output pin.
O This clock is obtained by 1/2 frequency-dividing SYSCLK.
Used only in the 16-bit pixel data mode.
– Digital ground
O V.sync signal output
H.sync signal output
O
The functions of this pin are selected by Pin 64 XIICEN.
When the XIICEN pin is "H", sets into the SONY SIO mode, and becomes the S0 serial-
O
out output pin.
When the XIICEN pin is "L", this pin is not used and sets into high impedance.
Field ID output.
When control register bit "FDS"="1", "L" indicates the first field and "H" indicates the
O second field.
When control register bit "FDS"="0", "H" indicates the first field and "L" indicates the
second field.
Digital power supply
–
Serial interface mode selection input pin. Pulled-up.
When "L", Pins 48 to 50, and 61 set into the I
O
When "H", Pins 48 to 50, and 61 set into the SONY SOP mode.
— 72 —
Function
2 C-BUS mode.