Noise Canceller Circuit - Hitachi H8/3637 Hardware Manual

9.4.3

Noise Canceller Circuit

The noise canceller circuit built into the H8/3637 Series is a digital low-pass filter that rejects
high-frequency pulse noise in the input at the input capture pin. The noise canceller circuit is
enabled by the noise canceller select (NCS)* bit in port mode register 2 (PMR2).
Figure 9.7 shows a block diagram of the noise canceller circuit.
Sampling clock
Input capture
D
signal
latch
Sampling clock
The noise canceller consists of five latch circuits connected in series, and a match detection
circuit. When the noise canceller function is disabled (NCS = 0), the system clock is selected as
the sampling clock. When the noise canceller is enabled (NCS = 1), the internal clock selected by
bits CKS1 and CKS0 in TMG becomes the sampling clock. The input signal is sampled at the
rising edge of this clock pulse. Data is considered correct when the outputs of all five latch circuits
match. If they do not match, the previous value is retained. Upon reset, the noise canceller output
is initialized after the falling edge of the input capture signal has been sampled five times.
Accordingly, after the noise canceller function is enabled, pulses that have a pulse width five times
greater than the sampling clock will be recognized as input capture signals.
If the noise canceller circuit is not used, the input capture signal pulse width must be at least 2ø or
2ø in order to ensure proper input capture operation.
SUB
Note: Rewriting the NCS bit may cause an internal input capture signal to be generated.
C C
Q D Q D
latch latch
∆ t
∆
t: Selected by bits CKS1, CKS0.
Figure 9.7 Block Diagram of Noise Canceller Circuit
C C
Q D Q D
latch latch
C
Q
Match
detection
circuit
Noise
canceller
output
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