Lsi Pin Description（Lsi 端子機能表 - Yamaha Portatone PSR-S700 Service Manual

LSI PIN DESCRIPTION（LSI 端子機能表）
AK4385ET (X6040A00) DAC (Digital to Analog Converter) (PSR-S700) ...........................................29
AK4396VF-E2 (X8324A00) DAC (Digital to Analog Converter) (PSR-S900) ......................................29
AK5381VT-E2 (X5219A00) ADC (Analog to Digital Converter) (PSR-S900) ......................................32
DM9000AEP (X7029A00) LAN CONTROLLER .................................................................................33
HD6417727F160CV (X2890B00) CPU ...............................................................................................30
HD6417709SHF200BV (X2687B00) CPU (SH3) (PSR-S900) ............................................................31
M38044M4-C16FPU0 (X4406100) LED DRIVER/SWITCH SCAN .....................................................33
MB3516APF-G-BND-EF (X2314A00) RGB ENCODER (PSR-S900) ................................................37
S1L50553F21Y000 (X4195A00) GATE ARRAY (PSR-S900) .............................................................32
T6TZ2XBG-0002 (X7376B00) SWP51 (Tone Generator) ....................................................................34
µPD780031AYGK-N04 (X0031200) LKS ............................................................................................37
YGV628-VZ (X6356A00) RGB CONTROLLER AVDP7 (PSR-S900) .................................................36
YGV628B-VZ (X6356B00) RGB CONTROLLER AVDP7 (PSR-S900) ..............................................36
AK4385ET (X6040A00) DAC (Digital to Analog Converter) (PSR-S700)
PIN
NAME I/O
NO.
1 MCLK I Master C ock
2 BICK I Aud o Ser a Data C ock
3 SDTI I Aud o Ser a Date Input
4 LRCK
I L/R C ock
5 PDN I Power Down mode
6 CSN I Ch p Se ect
7 CCLK I Contro Data Input
8 CDTI
I Contro Data Input
AK4396VF-E2 (X8324A00) DAC (Digital to Analog Converter) (PSR-S900)
PIN
NAME I/O
NO.
1 DV - D g ta ground
SS
2 DV - D g ta power supp y +3.3 V
DD
3 I Master c ock nput
MCLK
4 I Power-down mode
PDN
5 I Aud o ser a data c ock
BICK
6 I Aud o ser a data nput
SDATA
7 I L/R c ock
LRCK
8 I Soft mute/Ch p se ect
SMUTE/CSN
9 DFS0/CAD0 I Sampling speed mode select/Chip address 0
10 DEM0/CCLK I De-emphas s enab e 0/Contro data c ock
11 DEM1/CDTI I De-emphas s enab e 1/Contro data nput
12 I
DIF0
13 I D g ta nput format
DIF1
14 I
DIF2
FUNCTION
FUNCTION
PIN
I/O
NAME
NO.
9 AOUTR- O
Rch Ana og out(-)
10 AOUTR+ O Rch Ana og out(+)
11 AOUTL- O Lch Ana og out(-)
AOUTL+ O
12 Lch Ana og out(+)
13 Vss -
Ground
14 VDD - Power Supp y
15 DZFR O Rch Data Zero Input Detect
DZFL O
16 Lch Data Zero Input Detect
PIN
NAME I/O
NO.
15 TTL I CMOS/TTL eve se ect
16 VREFL I Low eve vo tage reference nput
17 VREFH I H gh eve vo tage reference nput
18 AV - Ana og power supp y +5 V
DD
19 AV - Ana og ground
SS
20 AOUTR- O Rch negat ve ana og output
21 AOUTR+ O Rch pos t ve ana og output
22 AOUTL- O Lch negat ve ana og output
23 AOUTL+ O Lch pos t ve ana og output
24 VCOM O Common vo tage output
25 P/S I Para e /ser a se ect
26 TST1/DZFL O Test 1/Lch zero nput detect
27 TST2/CAD1 I Test 2/Ch p address 1
28 ACKS/DZFR I/O Master clock auto setting mode/Rch zero input detect
PSR-S700/PSR-S900
DM: IC400
FUNCTION
DM: IC318
FUNCTION
29