Buck For Lpddr3 Core And Ebi Pad - LG -H815 Service Manual

16 15 14
L
< 4-1-11-1_PMIC_PM8994_Data >
PMIC_Option
K
J
OPT_2 Power-on sequence
GND TBD
Hi-Z TBD
VDD PMIC will power-down
I
H
QCT ref schematic revB
G
R4114
DNI
DNI(100K,1%)
C4105
C4104
DNI 1n
DNI(0.1u)
F
E

Buck for LPDDR3 Core and EBI pad

D
C
B
A
LGE Internal Use Only
16 15 14
13 12 11
+VPWR
PM_OPTION2
REV.C
JTAG_PS_HOLD|MSM_PS_HOLD
TP4105
115
MSM_PS_HOLD
130
PHONE_ON_N
D4100 R4106 191
DNI
177
131
VOL_DOWN_N
D4101 TP4101 148
PMI8994_SYSOK
162
PM_PON_RESET_N
118
+VPWR
185
63
155
+1V8_VREG_S4A
163
154
VCOIN
169
+1V225_VREG_LPDDR
153
168
VREF_LPDDR3_CA
184
139
68
WTR0_XO_IN
53
69
LNBBCLK_CXO2
QCT ref schematic revB
TP4102 22
BBCLK1_EN
54
BBCLK1_CXO
TP4104 70
TP4103
removed(33 ohm) 72
SLEEP_CLK
66
96
X4100 81
X1E0002910001
4 3
Thermistor XTAL2
1 2
XTAL1 GND/Therm
23
C4106 1u
19.2MHz
38
C4109 1u
83
Place caps close to PMIC
REV.B 51
VREG_XO is PM8994 VREG_L7
VREG_RF_CLK is PM8994 VREG_L5
CONNECT GND FROM PIN TO CAPACITOR,
THEN TO SYSTEM GND
+VPWR
1.3mm
A1
VIN1
B1
VIN2
C1
VIN3
D2
AUX_PMIC_PON EN
E3
VOUT
D3 A2
APPS_I2C_SDA U4950
SDA SW1
B2
SW2
FAN53526UC106X
E2
APPS_I2C_SCL
SCL
A3
PGND1
D1 B3
LPDDR3_VSEL VSEL PGND2
C2
PGND3
C3
AGND1
E1
AGND2
13 12 11
10 9 8
Rev_0.3
PM_OPTION2 PMIC_SPMI_CLK
PMIC_SPMI_DATA
88
PS_HOLD GPIO_01
42
KPD_PWR_N GPIO_02
41
CBL_PWR_N GPIO_03 VOL_UP_N
26
PON_1 LPG_DRV1/GPIO_04 SLIMPORT_CBL_DET
104
RESIN_N LPG_DRV2/GPIO_05 ANX_PDWN_CTL
102
SHDN_N BAT_ALARM_IN/GPIO_06
86
SLIMPORT_AVDD_EN
LPG_DRV3/GPIO_07
40
PON_RESET_N LPG_DRV4/GPIO_08 SD_CARD_DET
190
LPG_DRV5/GPIO_09
174
VPH_PWR LPG_DRV6/BB_CLK2_EN/GPIO_10
159
VPH_PWR_2 RF_CLK1_EN/GPIO_11
144
VDD_SNS RF_CLK2_EN/GPIO_12 Check QCT rev.B ref Schematic
189 C4100
LN_BBCLK_EN/GPIO_13
188
VDD_MSM_IO CHGR_INT/GPIO_14
82p
158
DIV_CLK1/SLEEP_CLK2/GPIO_15 CODEC_MCLK
143 R4109 51
PMI_CLK_IN
VCTRL DIV_CLK2/SLEEP_CLK3/GPIO_16
187 TOL=0.01
DIV_CLK3/SLEEP_CLK4/GPIO_17
172 R4108 0
VCOIN DIV_CLK4/SLEEP_CLK5/GPIO_18 WIFI_SLEEP_CLK
157
EXT_REG_EN1/GPIO_19
142
VREF_DDR EXT_REG_EN2/GPIO_20 PMI_SPON
141
BAT_ALARM_OUT/BAT_ALARM_IN/GPIO_21 BAT_LOW_ALARM
126
VREF_EBI0_CA GPIO_22
VREF_EBI1_CA
110
R4110 100K
AMUX_PU1 +1V8_VREG_L8A
U4100 TOL=0.01
VREF_EBI0_DQ
79
R4111 DNI
VREF_EBI1_DQ AMUX_HW_ID
PM8994
50
RF_CLK1 AMUX_0
PM_USB_ID
65
RF_CLK2 AMUX_1
80
AMUX_2
111
LN_BB_CLK AMUX_3 PA_THERM_0
94
AMUX_4
49
BB_CLK1_EN AMUX_5
BB_CLK1
116
BB_CLK2 VREF_PADS/MPP_01 SDC_UIM_VREF
85
US_EURO_HS_SEL/MPP_02
39
SLEEP_CLK VREF_DAC/MPP_03 VREF_DAC_MPP_3
55
HDMI_EN/MPP_04
161
VREF_XO_THERM SPKR_BOOST_EN/MPP_05
192
XO_THERM ENET_RST_N/MPP_06 LPDDR3_VSEL
160
GND_XOADC MPP_07 AUX_PMIC_PON
145
PRIVACY_LED/MPP_08
7
XTAL_19M_IN
6 Even number MPPs can be configured for current sinks, up to 40 mA in 5 mA
XTAL_19M_OUT
Odd number MPPs can be configured for output voltage buffers
117
VREG_XO AVDD_BYP C4107 1u
132
GND_XO DVDD_BYP C4108 0.1u
8 156
VREG_RF_CLK REF_BYP C4110 0.1u
140
GND_RF GND_REF
GND_CLKS_XO
CONNECT GND FROM PIN TO CAPACITOR,
THEN TO SYSTEM GND
REV.D
3mm
L4950
+1V225_VREG_LPDDR
330n
Rev.10 add
10 9 8
81
7 6 5 4
R4109 and C4100 are required and must be installed by default for FM radio
support. Otherwise, R4109 can be replaced with 0-ohm and C4100 can be DNIed.
The RC low-pass filter only needs to be installed if the 9.6 MHz MCLK output
frequency is found to be causing desense to RF/GPS performance.
PCB_Revision
0 100K 20K 0.300
A 100K 27K 0.383
B
100K 39K 0.505
C
100K 51K 0.608
D
100K 75K 0.771
E
100K 100K 0.900
F 100K 130K
1.017
1.0 100K DNI 1.800
1.1 100K
4/24 _ Please check thermistor Circuit
This schematic doesn't include voltage divider circuit
BACKUP BATTERY
Rev.B
BAT4100
L4956
VCOIN
47n
Rev.B
C4103
DNI
7 6 5 4
3 2 1
L
K
J
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H
G
F
E
D
C
B
LG Electronics
A
TITLE
H815
SIZE REV
DWG NO
PDM NUMBER
A2 Rev
DRAWN BY SHEET of 25 Date
User Name Drawing Date
4-1 PMIC_PM8994_Data
3 2 1