Multimedia Processor & Clock Generator - Sony VTX-D800U Service Manual

A B C
B..-VTX-D800
+3V3
C264
0.1
1
C265
0.1
Ground stiching for
C270 0.1 3.3V Close to Power
Plane
STP0_CLK,STP0_DAT[0-7],STP0_EN
C266 0.1
For Front and Side of PCB
C267 0.1
C269 0.1
0.1
C268
2
C209 C207 C246 C206
0.1 1
0.1 0.1
16V 6.3V
16V 16V
C247 C213 C244
4.7 0.1 0.1
+2V5 16V 16V
10V
C223
C210 C214 C245 C220
0.1 0.1 1 0.1 0.1
16V 16V 6.3V 16V 16V
C248
4.7
10V
+1V5
3
C249 C230
C211 C215 C224 C227 C251 C252
4.7 0.1 1 0.1 1 0.1
0.1 0.1
6.3V
10V 16V 16V 16V 16V 6.3V 16V
R260 R261 R262 R202
R263
XX
XX XX XX 10k
JTAG CONFIGURATION
JTRST
4
FOR NORMAL JTAG:-
FIT R256, R257, R258, R259, R202.
NO-FIT R260, R261, R262, R263, R203.
FOR EJTAG:-
R259
R256 R257 R258 R203
10k 10k 10k 10k XX
1/10W 1/10W 1/10W
FIT R260, R261, R262, R263, R203
NO-FIT R256, R257, R258, R259, R202.
+3V3
L200 C212 C217
C263 C250 C218
C208 100uH
100 4.7 1 0.1 0.01
4.7
6.3V 16V
5 10V 10V 25V
10V
PLACE CLOSE TO IC201
ALRCK
R265
47
1/10W
ABCK
R266
47
1/10W
ADO
R267
47
1/10W
AMCK
6
R268
ALRCK,ADO,ABCK,AMCK
47
1/10W
7 27MHz CLOCK GENERATION
R273
0 R274
0
CLK27M
R200
R275
XX 33
1/10W
C200
XX
C203
0.1
16V
8 7 6 5
IC200
8
FS6128-04
R201
1 2 3 4
10k
PWM_OUT
C201 XX
C260
0.1
16V
C259
+3V3
4.7
10V
FB200
0uH
C204
C202 C216
0.1 1000p
0.1
16V
16V
9
C260 TO BE PLACED CLOSE
TO PIN 2, IC200
DADD[0-12]
PLACE R200 AND R273 -> R275 CLOSE DQ[0-15]
TO PINS 5 & 6 RESPECTIVELY
RDATA[0-15]
R273 -> R275 ARE PROVIDED AS LINK
OPTIONS FOR THE ICS3721 DBA0,DBA1,DCASB,DCLK,DCLKB,DCSB,DQM0,DQM1,DQS0,DQS1,DRASB,DVREF,DWEB
10
11
D E F
C219 C222
1 0.1
6.3V 16V
204 203 202 201 200 199 198 197
C255 C254 205 VDD1
1 0.1
206 GND
6.3V 16V
207 GND
0.1
C232 CBPC
208
0.1
C233
209 CBPD
0.1
R206 C234
210 CBPE
4.7k 211 AGND4
STP0_EN
212 STP_EN / PMSINS
RDATA[11]
213 RDATA11
RDATA[5]
RDATA5
214
RDATA[12]
215 RDATA12
NALE
NALE
216 NAND_ALE
SPDIF 217 ATX
R264 47
218 ADO
STP0_DAT[1]
219 STP_DAT1
STP0_DAT[4]
220 STP_DAT4 / PMSSCLK
STP0_DAT[6]
221 STP_DAT6 / PMSPON
222 TEST
R208 100
SDA_0 223 SDA0
JTDI 224 JTDI
JTRST
225
RSTSWB
226 RSTSWB
VAR
227 VAR
228 AVDD1
229 AGND2
R204 10k 230 AVDD3
R205 4.7k AVDD4
231
232 AVDD5
233 OFF0/PPORT25
RDATA[4]
234 RDATA4
NCLE
NCLE
235 NAND_CLE
TXD_1B 236 TXD1B
237 ALRCK
238 ABCK
STP0_DAT[0]
239 STP_DAT0
STP0_DAT[3]
240 STP_DAT3
STP0_DAT[5]
241 STP_DAT5/PMSBS
TMODE2
TMODE2
242
JEDINT
243 EDINT
R209 100
SCL_0
244 SCL0
JTDO 245 JTDO
NMI 246 NMI
R242
247 EIVHS
4.7k
+3V3
C235
AGND1
0.1 248
249 CBPB
R241 4.7k 250 AVDD0
VACOMP 251 VACOMP
252 AVDD2
RDATA[3]
253 RDATA3
NRBB
NRBB
254 NAND_R/BB
255 GCSB1
RXD_1B 256 RXD1B
PWM_OUT 257 PWMOUT
258 AMCK
STP0_CLK
259 STP_CLK
STP0_DAT[2]
260 STP_DAT2
TMODE0
261 TMODE0
TMODE1
262 TMODE1
R243 100
SDA_1 263 SDA1
SCL_1 R244 100
SCL_1 264 SCL1
JTMS JTMS
265
RSTOUT
RSTOUT
266 RSTOUT
267 EIVVS
C236 0.1
268 CBPA
269 AGND0
VAG 270 VAG
271 AGND3
VAB
272 VAB
1 2 3 4 5 6 7 8
RDATA[0-15]
G H I
R272
XX
C238
0.1
196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153
IC201
UPD61120F1-100-JN1
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
GND
R271
10k
1/10W
GND
- 23 -
J K L M
RSTSWB
IR_IN_0B
152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137
AGND1_16 136
AVDD1_16 135
AVSYSCLKIN 134
GND
133
GND 132
GND 131
GND 130
GND 129
VDD1 128
RADD22
127
RADD16 126
RADD21 125
EVCK 124
SYSCLKIN 123
AVDD1_162 122
VDD1 121
VDD1 120
VDD1 119
VDD1 118
C261
C262 C239 C240
VDD2 117 0.1 0.1 0.1 1000p
16V
16V 16V 50V
VDD1
116
RADD12 115
RADD23 114
RADD15 113
AGND1_162 112
CLK27IN 111
AVDD1_266
110
VDD3 109
FCSB0 108
RADD25 107
RADD7 106
RADD24 105
MCLKIN 104
AGND1_266 103
AGND1_6 102
GND 101
VDD3 100
RADD5
99
PPORT28 98
RADD6 97
+3V3
VRCLKIN 96
AVDD1_6 95
SDIN 94
VDD1
93
GND 92
GRDYB
GRDYB 91
RADD4 90
PPORT31/OFF1 89
PPORT35 88
FCSB1 87
PPORT40 86
IRIN0 85
PPORT33/SMDAT1 84
RADD2 83
PPORT32/SMCLK1
82
R276
RADD3 81 XX
SCART_GPO_2
PPORT22/MMDOUT/DSR0B 80
STPERRB 79
PPORT42 78
PPORT41 77
DQ[1]
DQ1
76
DQ[3]
DQ3 75
DQ[5]
DQ5 74
DQ[7]
DQ7 73
MEMORY STICK INTERFACE
DWEB
DWEB 72
GND2 71
JL PIN
VDD2 70
GND2 69
JL219 MSINS
JL220 MSSCLK
52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
JL221 MSPON
JL215 MSBS
JL222 MSDIO
~ B Board Schematic Diagram [ Multimedia Processor & Clock Generator ] Page 1/6 ~
N
+3V3
+3V3
RSTSW
RSTSW
RSTSWB
Q201
DTC114YUA-T106
IR_IN_0
IR_IN_0B
Q202
DTC114YUA-T106
GND
GND
+1V5
FB205
0uH
C242
0.1
+3V3
16V
C241
4.7
10
DEBUG CONNECTOR
R282 R281
10k 10k
1 VCC
R280 R279 R240
10k 10k 10k
2 VCC
1/10W 1/10W 1/10W
JIG_MODE 3 JIG_MODE
CLK27M
CTS_1B CTS
4
RTS_1B
5 RTS
RXD_1B
6 RXD
TXD_1B
7 TXD
8 GND
CN202
8P
WHT
CN203
7P
1 GND
R252
10k RXD_2B E_RX_2
2
1/10W
RXD_3B E_RX_3
3
+3V3
TXD_3B E_TX_3
4
TXD_2B 5 E_TX_2
6 3V3_EMMA
7 PPORT35
R278
FCS1B
100
1/10W
AVS_INTB
IR_IN_0 +3V3
JIG_MODE
R253
10k
1/10W
SMARTLINK_TX
SIGNAL
MS INSERTED
SERIAL CLOCK
POWER ON
BUS STATE
DATA IO
B
1/6