JVC KD-SH9101 Service Manual page 36

4.2 AK7740VT (IC101) : Audio DSP with AD/DA converter
• Pin layout
• Block diagram
SDOUTA
SDINA
SDIN
RQ
SI
SO
SCLK
RDY
DRDY
JX
Note)
1-36 (No.49841)
AINL3 1
AINR2 2
AINL2 3
AINR1 4
AINL1 5
VREFH 6
AVDD 7
AVSS 8
DVSS 9
DVDD 10
XTI 11
XTO 12
Note) JX , SDIN and SDINA are Pull-down pins
LRCLK
LRCLK
OUTAE
SW3
SDINA
RQ
DSP
SDIN
SI
SO
SCLK
ISEL[2:0]
RDY
DRDY
SDOUTD1
JX
SDOUTD1
SDOUT
72kbit DLRAM
*SW1,SW2,SW3,ISEL[2:0],
OUTAE control register
C
A
When C is "L" (0) then A connects with Q
Q
B
36
35
34
33
32
31
48 pin LQFP
(TOP VIEW) 30
29
28
27
26
25
BITCLK CLKOUT XTI XTO SMODE
BITCLK CLKOUT XTI XTO SMODE
CONTROLLER
ADC
AINL-
AINL+
SW0
SDATA
AINR-
AINR+
SW2
SDATA
SW2
SDATA
SW1
AOUTL2
AOUTR2
BVSS
DVSS
DVDD
INT_RESET
S_RESET
RQ
SCLK
SI
SO
RDY
INT_RESET INT_RESET
S_RESET S_RESET
AINL-
AINL+
AINL1
AINL2
AINL3
AINL4
AINR-
AINR+
AINR1
AINR2
AINR3
AINR4
VREFF
VREFF
VCOM
AOUTL AOUTL1
DAC1
AOUTR AOUTR1
AOUTL AOUTL2
DAC2
AOUTR AOUTR2
SDOUT