Digital (Astro) Mode Of Operation; Controller Section; Figure 3-10. Controller Block Diagram - Motorola APX 3000 Basic Service Manual

Basic Theory of Operation: Digital (ASTRO) Mode of Operation
3.3

Digital (ASTRO) Mode of Operation

In the ASTRO (digital) mode of operation, the transmitted or received signal is limited to a discrete
set of frequency deviation levels. The receiver handles an ASTRO-mode signal identically to an
analog-mode signal, up to the point where the DSP decodes the received data. In the ASTRO
receive mode, the DSP uses a different algorithm to recover data.
In the ASTRO transmit mode, microphone audio is processed identically to an analog mode, with the
exception of the algorithm the DSP uses to encode the information. Using this algorithm, transmitter
FM deviation is limited to discrete levels.
3.4

Controller Section

The controller section
The main functional section consists of a dual core ARM and DSP controller, an encryption
processor (MACE), Flash memory, and a Double Data Rate Synchronous Dynamic Random Access
Memory (DDR SDRAM) and CPLD for GPIO expander multiple clock generation and SSI interface
for the radio system. The Power and Clocks section includes a power management IC (MAKO) and
various external switching regulators, and three clock sources (12 MHz and 24.576 MHz) from which
all other controller digital clocks are derived. The external audio section has a CODEC and 1W audio
PA (MAKO) to support accessories. The User Interface section provides communication and control
to a side connector interface conforming to GCAI (Global Communications Accessory Interface)
specifications. The GPS and Bluetooth section comprises of a Global Positioning Satellite(GPS),
Bluetooth combo chipset, an AVR Bluetooth controller IC, SDRAM, LF wakeup IC, Accelerometer IC
and MACE IC on the main board for secure communication control.
Battery Supply
POWER & CLOCKS
Clock sources:
12MHz,
24.576Mhz,
32.768kHz
Voltage Regulators
(See Figure 3-10.) comprises of five functional sections within the main board.
CONTROLLERS & MEMORY
ARM Processor
Digital Signal Processor
Flash Memory
DDR Memory
Encryption Processor
BT,GPS and Encryption
AVR
MACE
Accelerometer
GPS

Figure 3-10. Controller Block Diagram

Transceiver
3-7
USER INTERFACE
Side connector
Top Controller
AUDIO
Acc. Speaker
Acc. Microphone