Mask Option; I/O Memory Of Input Port - Epson E0C6006 Technical Manual

Cmos 4-bit single chip microcomputer
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

4.4.3 Mask option

An internal pull-up resistor can be selected for each of the eight bits of the input ports (K00–K03, K10–
K13). Having selected "pull-up resistor disabled", take care that the input does not float. Select "pull-up
resistor enabled" for input ports that are not being used.

4.4.4 I/O memory of input port

Table 4.4.4.1 shows the I/O addresses and the control bits for the input port.
Register
Address
D3
D2
REMSO IREM
0F0H
R/W
REMC
EIREM
0F2H
R/W
K03
K02
0FAH
R
K13
K12
0FBH
R
∗1
Initial value at initial reset
∗2
Not set in the circuit
K00–K03: Input port data (0FAH)
K10–K13: Input port data (0FBH)
The input data of the input port terminals can be read with these registers.
When "1" is read: High level
When "0" is read: Low level
Writing: Invalid
The value read is "1" when the terminal voltage of the input port (K00–K03, K10–K13) goes high (V
and "0" when the voltage goes low (V
EIK0, EIK1: Interrupt mask registers (0F2H•D0, D1)
Masking the interrupt of the input port terminal groups can be done with these registers.
When "1" is written: Enabled
When "0" is written: Masked
Reading: Valid
With these registers, masking of the input port bits can be done for each of the four-bit terminal groups.
At initial reset, these registers are all set to "0".
16
Table 4.4.4.1 Control bits of input port
∗1
D1
D0
Name Init
REMSO
0
IK1
IK0
∗4
∗5
IREM
∗4
IK1
0
R
∗4
IK0
0
REMC
1
EIK1
EIK0
EIREM
0
EIK1
0
EIK0
0
∗2
K03
K01
K00
∗2
K02
∗2
K01
∗2
K00
∗2
K13
K11
K10
∗2
K12
∗2
K11
∗2
K10
∗3
Always "0" being read
∗4
Reset (0) immediately after being read
). These bits are reading only, so writing cannot be done.
SS
1
0
On
Off
Forced REM output (on/off)
Yes
No
Interrupt factor flag (REM)
Yes
No
Interrupt factor flag (K10–K13)
Yes
No
Interrupt factor flag (K00–K03)
On
Off
REM carrier generation on/off
Enable
Mask
Interrupt mask register (REM)
Enable
Mask
Interrupt mask register (K10–K13)
Enable
Mask
Interrupt mask register (K00–K03)
High
Low
High
Low
K0 input port data
High
Low
High
Low
High
Low
High
Low
K1 input port data
High
Low
High
Low
EPSON
Comment
∗5 Undefined
DD
E0C6006 TECHNICAL MANUAL
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