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GC5328 Low-Power Wideband Digital Predistortion Transmit Processor
FEATURES
1
•
Integrated DUC, CFR, and DPD Solution
•
20-MHz Max. Signal Bandwidth, Based on Max.
DPD Clock of 200 Mhz, Fifth-Order Correction
•
DUC: Up to 12 CDMA2000/TDSCDMA, 4
W-CDMA, 2–10 MHz or 1–20 MHz OFDMA
Carriers
•
CFR: Typically Meets 3GPP TS 25.141 < 6.5 dB
PAR, < 8.5 dB PAR for OFDMA Signals
•
DPD: Short-Term Memory Compensation,
Typical ACLR Improvement > 20 dB
•
GC5328IZER PBGA Package, 23 mm × 23 mm
•
1.2-V Core, 1.8-V HSTL, 3.3-V I/O
•
2.5-W Typical Power Consumption
GC5328
BB Data
DUC-CFR-DPD
Host
'C6727
Control
DSP
Interface
DESCRIPTION
The GC5328 is a lower-power version of the GC5322 wideband digital predistortion transmit processor. The
GC5328 includes a digital upconverter (DUC) block, a crest factor reduction (CFR) block, a digital predistortion
(DPD) block, feedback (FB) block, and capture buffer (CB) blocks.
The GC5328 GPP block receives the interleaved IQ data from the baseband input. The individual IQ channels
are gain-adjusted in the GPP and routed to the DUC. The GPP and DUC can be bypassed to input a combined
IQ signal. The DUC provides three stages of interpolation and a complex mixer. There are two DUC blocks. The
output from the DUC blocks is combined in the sum chain. Each of the 1 to 12 DUC channels can be summed,
and the composite signal can be scaled.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Check for Samples:
DAC
I/Q
Modulator
DAC
ADC
Figure 1. GC5328 System Block Diagram
SLWS218A – OCTOBER 2009 – REVISED OCTOBER 2009
GC5328
•
TMS320C6727 DPD Optimization Software
•
Supports Direct Interface to TI High-Speed
Data Converters
APPLICATIONS
•
3 GPP (W-CDMA) Base Stations
•
3 GPP2 (CDMA2000) Base Stations
•
WiMAX, WiBRO, and LTE (OFDMA) Base
Stations
•
Multicarrier Power Amplifiers (MCPAs)
Attenuator
I/Q
0 31.5 dB
–
LO
Attenuator
Mixer
0 31.5 dB
–
Copyright © 2009, Texas Instruments Incorporated
GC5328
HPA
LPA
B0278-03
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Table of Contents
Related Manuals for Texas Instruments GC5328
Summary of Contents for Texas Instruments GC5328
- Page 1 (DPD) block, feedback (FB) block, and capture buffer (CB) blocks. The GC5328 GPP block receives the interleaved IQ data from the baseband input. The individual IQ channels are gain-adjusted in the GPP and routed to the DUC. The GPP and DUC can be bypassed to input a combined IQ signal.
- Page 2 DUCs in Active Only in Dual BB Clock Domain DPD Clock Domain 1-Chn Mode 2-Chn Mode 6-Chn Mode Antenna Mode B0279-03 Figure 2. GC5328 Functional Block Diagram Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5328...
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Page 3: Available Options
The GC5328 meets multicarrier 3G performance standards (PCDE, composite EVM, and ACLR) at PAR levels down to 6.5 dB and improves the ACLR, at the PA output, by 20 dB or more. The GC5328 integrates easily into the transmit signal chain between baseband processors (such as the Texas Instruments TMS320C64x™... -
Page 4: Baseband Clock Input
The GC5328 DUC block has interpolation filters, programmable delays, and complex mixers for each channel. There are two DUC blocks within the GC5328. The sum chain after the DUC channel combines the DUC channel streams or the bypass stream and sends the data to the CFR block. Each DUC can operate in one wide, two medium, or six CDMA channels. - Page 5 OUTPUT FORMATTER AND DAC INTERFACE (OFMT) The output format and DAC interface presents the GC5328 output in the proper format for the different output interfaces. The output formatter supports a test pattern for testing the DAC5682Z interface. The two output interfaces supported for the GC5328 are: •...
- Page 6 PullDown SYNCP, SYNCN B0371-01 (1) ExtTerm – see DAC data sheet. (2) ExtPullup, 500 Ω to 1.8 V, only required when DAC Data Clock > 337 MHz Figure 4. GC5328 to DAC5682Z Interface GC532x DAC5688 DPD Clock DAC Clock CLKIN, CLKINC...
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Page 7: Feedback Path (Fb)
The MPU interface is designed to interface with external memory interface (EMIF) ports on TI DSPs operating in asynchronous mode. It consists of a 16-bit bidirectional data bus, a 10-bit address bus, and RDB, WRB, OEB, and CEB control signals. The CEB and OEB signals to the GC5328 require additional logic outside the TMS320C6727B; see Table Table 1. -
Page 8: Capture Buffers (Scb)
Figure 7. 6727 DSP to GC5328 EMIF Interface CAPTURE BUFFERS (SCB) The GC5328 has two capture buffers of 4096 complex words. The capture buffers are normally used to capture the Tx reference signal and the feedback output signal. Capture buffer A can capture: •... -
Page 9: Input Syncs And Output Sync
The GC5328 features multiple user-programmable input syncs. There are three syncs sampled with the BBClock, (A, B, and C), and the Sync D,DC as an LVDS sync sampled by the DPD clock. Internally, the GC5328 can also generate timed and software-controlled syncs. The sync A input is required for the GC5328 hardware to initialize. -
Page 10: Pin Assignment And Descriptions
MFIO MFIO MFIO MFIO MFIO MFIO MFIO MFIO = Baseband Input = Signal Interface = Power and Biasing = Microprocessor Interface = Miscellaneous = JTAG Interface P0107-01 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5328... -
Page 11: Pin Functions
DAC bias, 50 Ω to VDDS ADCIREF ADC bias, 1 kΩ to VSS ADCVREF ADC bias to VDD BASEBAND INPUT BB[15:10] A16, D17, C17, B17, A17, D18 Baseband input signal Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5328... -
Page 12: Special Power-Supply Requirements For Vdda1, Vssa1, Vdda2, Vssa2
In particular, supply VDDA1 must be less than or equal to VDD1 when VDD1 is at the low end of the required range. The series resistor assures this condition is met. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5328... -
Page 13: Fb Input From Lvds Adc
LVDS SDR – ADS5544 ADCs are typically connected to the GC5328 so the MSB of the ADC is connected to FB port A MSB. The lower bit numbers follow until the ADC bits are all connected. Any remaining lower-order bits on the FB port should be terminated with resistors, P connection to GND, N connection to 1.8 V as a logic 0. -
Page 14: Mpu Interface Guidelines
(128-Mb) memory modules provided by Samsung (K4S641632H-TC(L)75), other memory alternatives are available. The use of an external inverter with minimal propagation delay is required for OEB of the GC5328; this device is necessary when using a TMS320C6727 DSP. Additional documentation for the hardware interface is available in the TMS320C672x Hardware Designer’s Resource Guide application report (SPRAA87) and TMS320C672x DSP... -
Page 15: Absolute Maximum Ratings
GPIO UPDATA[] INTROUT INTROUT UPADDRESS[] SelCode and CNTL CS2-1 B0374-01 Figure 9. DSP-to-GC5328 EMIF Interface Specifications ABSOLUTE MAXIMUM RATINGS VALUE UNIT Core supply voltage –0.3 to 1.32 Digital supply voltage for TX –0.3 to 2 Digital supply voltage –0.3 to 3.6... -
Page 16: Thermal Characteristics
(1) HSTL output levels measured at 675 Mb/s delay and with 100-Ω load from P to N. Drive strength set to 0x360. (2) 400-Mbps DAC signal, 200-Mhz DPD clock, maximum filtering, 70-Mhz BBPLL clock input Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5328... -
Page 17: Switching Characteristics
Q(ch = 1, t = 1) Q(ch = N, t = 1) I(ch = 1, t = 2) BB[15:0] su(BB) h(BB) BBFR T0284-01 Figure 10. Baseband Timing Specifications Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5328... -
Page 18: Dpd Clock And Fast Sync Switching Characteristics
(2) Jitter is based on a period of (1/(DPDClk × 2)) (for BUC Interp 1 or 2); (1/( DPDClk × 3)) (for BUC Interp 1.5 or 3). DPDCLK DPDCLKC SYNCDC SYNCD su(SYNCD) h(SYNCD) SYNCA SYNCB SYNCC su(SYNCA, -B, -C) h(SYNCA, -B, -C) T0286-01 Figure 11. DPD Clock and Fast Sync Timing Specifications Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5328... -
Page 19: Mpu Switching Characteristics (Read)
(1) Controlled by design and process and not directly tested. HIGH(RD) h(OEB) su(OEB) su(CEB) su(AD) ADDR 3-State DATA d(RD) Z(RD) h(RD) T0287-01 Figure 12. MPU READ Timing Specifications Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5328... -
Page 20: Mpu Switching Characteristics (Write)
Time CEB or WRB must remain HIGH between WRITEs OEB and RDB are HIGH high(WR) low(WR) high(WR) h(WR) su(WR) ADDR DATA T0288-01 Figure 13. MPU WRITE Timing Specifications Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5328... -
Page 21: Jtag Switching Characteristics
= (BUC Interp × DPDClk / 2). CLK(DAC) (2) t data clock-to-data is measured during characterization. SKW(DAC) CLK(DAC) DACCLKC DACCLK DAC[15:0]P DAC[15:0]N SKW(DAC) T0290-01 Figure 15. TX Timing Specifications (HSTL – DDR) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5328... -
Page 22: Envelope Switching Characteristics
(1) Envelope output is magnitude; this is a real output at a DPDClk/2 (100-MHz) rate. (2) t and t data clock-to-data is measured during characterization. ENVCLK ENVDATA[15:0] T0449-01 Figure 17. Envelope Timing (MFIO – CMOS 3.3 V) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5328... -
Page 23: Lvds Switching Characteristics
. For port B h(ADCB[#/2]P) (1) Specifications are limited by GC5328 performance and may exceed the example ADC capabilities for the given interface. (2) Setup and hold measured for ADC[15:0]P, ADC[15:0]N valid for (VOD > 250 mV) to/from ADCCLK and ADCCLKC clock crossing (VOD = 0). -
Page 24: Glossary Of Terms
Decibels relative to 1 mW (30 dBm = 1 W) Dual data rate (ADC output format) Digital signal processing or digital signal processor Digital upconverter (usually provides the GC5328 input) Error vector magnitude Finite impulse response (type of digital filter) -
Page 25: Packaging Information
PACKAGE OPTION ADDENDUM www.ti.com 12-Nov-2009 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Type Drawing GC5328IZER ACTIVE Pb-Free SNAGCU Level-3-260C-168 HR (RoHS) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. -
Page 27: Important Notice
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.