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2.7.8
Single-Halfword HPIC Cycle in 16-bit Multiplexed Mode
Figure 6
shows the special case (see
access the HPIC. The state of HHWIL is ignored and if a dual-halfword access is performed, then the
same HPIC register is accessed twice.
Figure 6. Multiplexed-Mode Single-Halfword HPIC Cycle (Read or Write)
HCS
Internal
HSTRB
HR/W
HCNTL[1:0]
HD[15:0]
HRDY
HHWIL
2.7.9
Hardware Handshaking Using the HPI-Ready (HRDY) Signal
The HPI uses its ready signal, HRDY, to tell the host whether it is ready to complete an access. During a
read cycle, the HPI is ready (drives HRDY high) when it has data available for the host. During a write
cycle, the HPI is ready (drives HRDY high) when it is ready to latch data from the host. If the HPI is not
ready, it can drive HRDY low to insert wait states. These wait states indicate to the host that read data is
not yet valid (read cycle) or that the HPI is not ready to latch write data (write cycle). The number of wait
states that must be inserted by the HPI is dependent upon the state of the resource that is being
accessed.
When the HPI is not ready to complete the current cycle (HRDY low), the host can begin a new host cycle
by forcing the HPI to latch new control information. However, once the cycle has been initiated, the host
must wait until HRDY goes high before causing a rising edge on the internal strobe signal (internal
HSTRB) to complete the cycle. If internal HSTRB goes high when the HPI is not ready, the cycle will be
terminated with invalid data being returned (read cycle) or written (write cycle).
One reason the HPI may drive HRDY low is a not-ready condition in one of its first-in, first-out buffers
(FIFOs). For example, any HPID access that occurs while the write FIFO is full or the read FIFO is empty
may result in some number of wait states being inserted by the HPI. The FIFOs are explained in
Section
2.7.10.
The following sections describe the behavior of HRDY during HPI register accesses. In all cases, the chip
select signal, HCS, must be asserted for HRDY to go low.
SPRUF87A – October 2007 – Revised May 2008
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Section
2.7.6) when the host performs a single-halfword cycle to
Valid
00
Data 1
Valid
Peripheral Architecture
Host Port Interface (HPI)
21
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