Holding Circuit For Power Failure By Temporary Memory; Use Of The Latch Unit Kl6L; Latch Switch Qn With K2Cpu - Mitsubishi Electric melsec-k Programming Manual

5-2-9. Holding circuit for power failure with temporary memory
(1) Use of the latch unit KL61
Installation of KL61 to the I/O unit No. 5 as a 16 point latch taking power failure holding
output from output Y60 connected to the I/O unit No. 6.
Fig. 5-22. Latch circuit by latch unit
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Step
No. Instructior
1
Device No.
Latch switch ON with K2CPU
Collective holding at the time of power failure is executed by the latch switch for the tem-
porary memories M128 to 253.
Fig. 5-23. Latch circuit by temporary memory (for K2CPU)
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