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APPENDIX
IC DESCRIPTION
Pin
Pin Name
No.
10
656IO7
11
VSSP2
12
VDDP2
13
SCL
2)
14
V
15
656IO6
16
656IO5
17
HOUT
3)
18
H50
19
ADR / TDI
4)
20
V50
21
656IO4
22
656IO3
23
VOUT
24
RESET
25
VDDP3
26
VSSP3
27
CLKOUT
28
VDDD3
29
VSSD3
30
656IO2
31
656IO1
32
656IO0
33
VSSD4
34
VDDD4
35
VDDAFBL
36
VSSAFBL
37
FBL1
38
FBL2
Type
Connection
(If not used)
I/O
Leave open
S
S
I
I
Connect to
vss
I/O
Leave open
I/O
Leave open
O
Leave open
O
Leave open
I
O
Leave open
I/O
Leave open
I/O
Leave open
O
Leave open
I
S
S
O
Leave open
S
S
I/O
Leave open
I/O
Leave open
I/O
Leave open
S
S
S
S
I
Connect to
vss
I
Connect to
vss
8
Short Description
Digital input / output (MSB)
Supply voltage for digital (0 V pad)
Supply voltage for digital (3.3 V pad)
2
I
C-Bus clk
Vertical pulse for RGB input
Digital input / output
Digital input / output
Horizontal output (Single or double scan, depen-
dent on version)
Hout 50 Hz (with skew)
2
I
C address / test data in
Vout 50 Hz
Digital input / output
Digital input / output
Vertical output (Single or double scan, dependent
on version)
Reset input (Reset when low)
Supply voltage for digital (0 V pad)
Supply voltage for digital (3.3 V pad)
Output clock (27 MHz nom.)
Supply voltage for DRAM (1.8 V digital)
Supply voltage for digital (0 V digital)
Digital input / output
Digital input / output
Digital input / output (LSB)
Supply voltage for digital (0 V digital)
Supply voltage for digital 1.8 V digital
Supply voltage for FBL (1.8 V)
Supply voltage for FBL (0 V)
Fast Blank input 1 (H1) (Analog input)
Fast Blank input 2 (H2) (Analog input)
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