Memory Description; Read Cycle - Nokia 616 Service Manual

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Memory description

The TF4 baseband consists of 64Mbit (8MB) external flash memory. Access to the flash is
performed as 16-bit access in order to improve the data rate on the bus.
The purpose of the memory interface is to reduce the amount of connections by multi-
plexing the address and data bus on to the same signals. If the memory address space is
more than 16 bits, which is the case, then 16-bit data can be multiplexed on the address
inputs. This requires the memory to store the address during the first cycle in the access
as described in Figure 10.
In addition to this, the system provides a Power Save signal (PS), which is used to reduce
the switching on the external bus between the memory and the UPP. In case of writing to
the flash, the UPP provides the information on the PS signal, and in case data is read
from the flash, the memory provides the status of the PS signal. The PS signal is used to
indicate if data should be inverted at the receiver end. If PS = "1" the data shall be
inverted at the receiver end before it is stored/processed. The PS-signal will be described
more in details in section Power saving signal (PS).
Furthermore the memory is capable of handle burst-mode (multiplexed address/data-
bus) and memory blocking, which is controlled by the UPP.

Read cycle.

The read cycle is initiated by first applying the address to the multiplexed address/data-
bus. The address is latched at the rising edge of the AVD-signal. The memory device cap-
Issue 2.0 Mar/2005
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