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1. Description
1.3 Principle of operation
The program memory contains the STEP 5 program written by the
user. The memory is organized bytewise, one byte comprising 8 bits
and 2 bytes constituting a complete statement, e.g. A 1 5.1. This
statement implies the following:
-Examine input 15.1 to see whether it is "1 " and AND this signal
with the result of the previous scanning operation.
The statements contained in the program memory are executed
consecutively and cyclically by the processor. The individual mem-
ory locations are referenced by an address counter. By increment-
ing the address counter by +l, it is possible to read out the next
two bytes (a complete statement).
The following is a description of the principle of operation of the PC
by way of example of the A1 5.1 and
=
Q 5.3 statements (see Fig. 5).
When the address counter of the processor reaches the appropri-
ate memory location, the "AI 5.1" statement stored there is read
out.
The parameter 5.1 is output via the address bus to all I10 modules,
where it is decoded by the address decoders.
The operation decoder of the CPU evaluates the operand "I" and
holds all output modules disabled via the enabling bus.
In conjunction with the full parameter, therefore, input 5.1 is
specified and can be examined. ?pending
on the signal status at
the input of this element, either 1" or "0" is transmitted on the
input data bus (DIN) to the sequence logic unit of the processor for
further processing.
From the bit pattern for the letter "A" in the operation "AI" (A
=
AND), the decoder recognizes that the result of the scan has to be
ANDed with the result of the previous scanning operation in the
logic unit.
The new RLO (result of logic operation) is stored in the logic unit.
The next statement, in this case
"=
Q5.3", is read out by incre-
menting the address counter again. The address 5.3 is output via
the address bus to all I10 modules, where it is decoded.
The decoder evaluates the operand
"=
Q" and places the result of
the logic operation (RLO) stored in the logic on the output data bus
(DouT). After enabling of the I10 modules, the RLO is available at
output Q5.3. Due to the cyclic execution of the statements, the
output statuses must be stored on the output module.
Program memory
(EPROM)
Address counter
11000
8
00100000101 Statement
r,2e
= Q
5
3
1
i
Operation
I
Dour
1
1
1
DIN
F
T
l
7
T-\
I
Input 15.1
Output Q5.3
Fig. 5 Principle of operation of the
S5OlOW
programmable controller
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