Pin Description - Philips DVDR5350H/02 Service Manual

PIN DESCRIPTION

Mnemonic Input/Output
DGND G
AGND G
CLKIN_A I
CLKIN_B I
COMP1, O
COMP2
DAC A O
DAC B O
DAC C O
DAC D O
DAC E O
DAC F O
P_HSYNC I
P_VSYNC I
P_BLANK I
S_BLANK I/O
S_HSYNC I/O
S_VSYNC I/O
Y7 to Y0 I
C7 to C0 I
S7 to S0 I
RESET I
R , R I
SET1 SET2
SCLK I
SDA I/O
ALSB I
V P
DD_IO
V P
DD
V P
AA
V I/O
REF
EXT_LF I
RTC_SCR_TR I
2
I C I
GND_IO
TEST0 to I
TEST5
Circuit- and IC description
p
Function
Digital Ground.
Analog Ground.
Pixel Clock Input for HD (74.25 MHz Only, PS Only (27 MHz), SD Only (27 MHz).
Pixel Clock Input. Requires a 27 MHz reference clock for progressive scan mode or a 74.25 MHz (74.1758
MHz) reference clock in HDTV mode. This clock is only used in dual modes.
Compensation Pin for DACs. Connect 0.1 μF capacitor from COMP pin to V
CVBS/Green/Y/Y Analog Output.
Chroma/Blue/U/Pb Analog Output.
Luma/Red/V/Pr Analog Output.
In SD Only Mode: CVBS/Green/Y Analog Output; in HD Only Mode and Simultaneous HD/SD Mode:
Y/Green [HD] Analog Output.
In SD Only Mode: Luma/Blue/U Analog Output; in HD Only Mode and Simultaneous HD/SD Mode: Pr/Red
Analog Output.
In SD Only Mode: Chroma/Red/V Analog Output; in HD Only Mode and Simultaneous HD/SD Mode:
Pb/Blue [HD] Analog Output.
Video Horizontal Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.
Video Vertical Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.
Video Blanking Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.
Video Blanking Control Signal for SD Only.
Video Horizontal Sync Control Signal for SD Only.
Video Vertical Sync Control Signal for SD Only.
SD or Progressive Scan/HDTV Input Port for Y Data. Input port for interleaved progressive scan data. The
LSB is set up on Pin Y0.
Progressive Scan/HDTV Input Port 4:4:4 Input Mode. This port is used for the Cb [Blue/U] data. The LSB is
set up on Pin C0.
SD or Progressive Scan/HDTV Input Port for Cr [Red/V] data in 4:4:4 input mode. LSB is set up on Pin S0.
This input resets the on-chip timing generator and sets the ADV7322 into default register setting. RESET is
an active low signal.
A 3040 Ω resistor must be connected from this pin to AGND and is used to control the amplitudes of the
DAC outputs.
I 2 C Port Serial Interface Clock Input.
2
I C Port Serial Data Input/Output.
TTL Address Input. This signal sets up the LSB of the I
activated, which reduces noise on the I
Power Supply for Digital Inputs and Outputs.
Digital Power Supply.
Analog Power Supply.
Optional External Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
External Loop Filter for the Internal PLL.
Multifunctional Input. Real time control (RTC) input, timing reset input, subcarrier reset input.
This input pin must be tied high (V
Digital Input/Output Ground.
Not used. Tie to DGND
3139 785 31532
2
C address. When this pin is tied low, the I
2
C interface.
) for the ADV7322 to interface over the I
DD_IO
9. EN 183
.
AA
2
C filter is
2
C port.