Memory Circuit Control - Fujitsu Impact 3650 Maintenance Manual

5.3.2.2 Memory Circuit Control

Figure 5.3.7 is a memory circuit control block diagram.
MB90706
External bus
DRAM control
Chip select address
decoder
I/O port
The MB90706 has the DRAM control and chip select address decoder circuits for memory control as shown in
Figure 5.3.7
[DRAM control]
The DRAM control outputs DRAM control signals RAS and CAS to control DRAM data reading and writing and
refresh DRAM.
[Chip select address decoder]
The chip select address decoder decodes addresses and outputs a chip enable signal to ROM.
The memory circuit consists of four types of elements, DRAM, PROGRAM ROM, and EEPROM as shown in
Figure 5.3.7.
[DRAM]
The MB90706 has a "256K x 16 bits" DRAM for control program work areas, line buffers, and external character
storage areas.
RAS,CAS,
CS0
EEPROM
16K Bits
Figure 5.3.7 Memory control block diagram
DRAM
256k×16 Bit
PROGRAMROM
1M×16 Bit
135
Defined space capacity
Max. 1M Bytes
Max. 4M Bytes