Toshiba SD-1300A Service Manual page 67

Table 3-5-4 TMP94C251AF(Z) (4/5)
Pin
Name
No.
24 PF4 Port F4: I/O port
TXD1 Serial transmission data 1 (open drain
output is possible)
25 PF5 Port F5: I/O port
RXD1 Serial reception data 1
26 PF6 Port F6: I/O port
CTS1 Serial transmission is possible 1
SCLK1 Serial clock I/O 1
131 PG0~PG7 Port G: Input port
| AN0~AN7 Analog input: Enters 10 bit AD converter
138
3 DAOUT0 DA output 0: Develops 8 bit DA converter 0
4 DAOUT1 DA output 1: Develops 8 bit DA converter 1
126 PH0 Port H0: I/O port
TC0 Terminal count 0: Develops "H" level with
strobe when micro DMA channel 0 counts
0.
127 PH1 Port H1: I/O port
TC1 Terminal count 1: Develops "H" level with
strobe when micro DMA channel 1 counts
0.
128 PH2 Port H2: I/O port
TC2 Terminal count 2: Develops "H" level with
strobe when micro DMA channel 2 counts
0.
129 PH3 Port H3: I/O port
TC3 Terminal count 3: Develops "H" level with
strobe when micro DMA channel 3 counts
0.
125 PH4 Port H4: I/O port (schmitt input)
INT0 Interrupt request terminal 0: Terminal for
interrupt request signal of which rising/
falling edge is programmable. (schmitt
input)
117 PZ0~PZ7 Port Z: I/O port
|
124
28 NMI Non maskable interrupt request terminal:
Terminal for interrupt request signal at the
falling edge. Depending on the program,
interrupt request signal at rising edge may
be used. (schmitt input)
42 WDTOUT Watch dog timer output terminal
30, AM0~1 Address mode: Selects the starting
40 external data bus width after releasing the
reset
AM1 = "0", AM0="0": starting at the 8 bit
external data bus
AM1 = "0", AM0="1": starting at the 16 bit
external data bus
AM1 = "1", AM0="0": Do not set.
AM1 = "1", AM0="1": Do not set.
32, TEST0~1 Test: Used to "GND"
33
31 CLK Clock: Develops System clock
38, X1/X2 Oscillator connection terminal
39
41 RESET Reset: Device is initialized.
(With the pull-up resistance) (schmitt input)
139 VREFH Reference voltage input terminal for 10 bit
AD converter (H)
140 VREFL Reference voltage input terminal for 10 bit
AD converter (L)
1 DAREFH Reference voltage input terminal for 8 bit
DA converter (H)
2 DAREFL Reference voltage input terminal for 8 bit
DA converter (L)
Function
3-25
Table 3-5-4 TMP94C251AF(Z) (5/5)
Pin
Name
No.
142 ADVCC 10 bit AD converter power supply terminal
141 ADVSS 10 bit AD converter GND terminal (0V)
144 DAVCC 8 bit DA converter power supply terminal
143 DAVSS 8 bit DA converter GND terminal (0V)
36 CLVCC Power supply terminal for clock doubler.
34 CLVSS GND terminal for clock doubler.
5, DVCC Digital power supply terminal (+5V)
27,
43,
61,
78,
88,
98,
116
14, DVSS Digital GND terminal (0V)
37,
54,
69,
87,
89,
107,
130
Function