System Control Block Diagram - JVC HM-DH30000U Service Manual

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4.36

SYSTEM CONTROL BLOCK DIAGRAM

5
CAP MDA
M
CON1
DRUM_CTL_V
DRUM MOTOR
3
2
1
M
4
LOADING
5 5
M
ROT AR Y
ENCODER
3
1 2
A/C HEAD
A/C HEAD
CN1
CTL HEAD ( - )
2
CTL CTL HEAD ( + )
1
TO
VIDEO/AUDIO
2
TO
AUDIO I/O
TO DIGITAL
(HOST)
CN7001
1
For ADJ.
A
MAIN ( SYSCON, MAIN-TERMINAL )
0 3
CN3003
CAP_REV ( L )
6
CAP_CTL_V 3
CAP_FG 2
WF1
WF2
CN3001
3
D.PG
4
D.FG
5
WF3
PC3001
PHOTO
SENSOR
IC3004
MOTOR
( LOADING MOTOR
SENSOR
VOLTAGE CONTROL )
CN3002
LDM2 2 9
2 LDM2 LMC1
LDM1 4 7
1 LDM1 LMC2
1
DRIVE
Vref
CONTROL
CN3004
LSB 1
LSC 2
LSA 3
CN2001
6
7
V. PULSE
VIDEO_ENV
V/STD/HS1.FF
A/HS2.FF
H.REC_ST(H)
N.REC_ST(H)
A.MUTE(H)
CN3009
HS2_FF 9 A/HS2.FF
HS1_FF V/STD/HS1.FF
8
REF30 7
REF5
6
HOST_RESET
5
KBUS_REQ
4
KBUS_CLK 3
KBUS_DATA 1
AL6V
CN3010
RESET 2
FWE 3
SIO 5 SIO
SII 6 SII
Note : For the waveforms in this block diagram, refer to page 4-67.
B C
IC3001
( SYSTEM CONTROL MICRO PROCESSOR )
OSC2 ( OUT )
28
CAP REV ( L ) OSC1 ( IN )
REC_SAFETY
101
CAPPWM
S.DATA TOSYS
8
CFG
S.DATA FRSYS
D_CASS(H)
END SENSOR
START SENSOR
102
DRUMPWM
I2C DATA
107
DPG
108
DFG
S_CASS(H)
54
SP FG HS_RECST(H)
PC3002
HS2_ENV
PHOTO 55
D_REC_LEVEL2
TU FG
D_REC_LEVEL1
D_ENV/HS1_ENV
CH1_RECST(H)
36
LMC1
CH2_RECST(H)
37
LMC2
38
VOL T AGE
LMC3
TP4001
Q3001
CTL.P
WF4
6
CTLAMPOUT
EXP_DATA1
26
LSB
EXP_CLK
27
LSC
25
LSA
Q4002
106
ES
HI_S_FF_REW
EXP_DATA2
3
CTL ( - )
1
CTL ( + )
WF5
104
NOT
M.PULSE
USED
110
V.PULSE
19
C. SYNC
VIDEO_ENV
100
D.FF/STD.FF/HS1.FF
99
A.FF/HS2.FF
87
H.REC_ST(H)
88
N.REC_ST(H)
89
A.MUTE(H)
EXP_DATA3
90
REF30
91
REF5
103
HOST_RESET
57
K-BUS-REQ
53
K-BUS-CLK
52
K-BUS-OUT
51
K-BUS-IN
D3004
2 1 66
RESET RES
IC3002
3
( RESET )
Q3013
I2C_DATA2
71
ES MODE
I2C_CLK2
62
FWE
Published in Heiloo Holland
D
4-69 4-70
65
X1 X3001
TIMER CLOCK
64
(32KHz)
X2
69 X3002
SIO
MAIN SYSTEM
67 CLOCK SII
(10MHz)
58
48
S.CLK
46
47
42
13 END
Q3003
SENSOR
I2C_DATA_A/V
17 START
I2C_CLK_A/V
Q3002
SENSOR
49
50
I2C CLK
56
S3002
S.CASS
83
18
41
A/HS2.FF
40
20
74
81
V/STD/HS1.FF
4
DRECL
5
DVHSL
6
HSH
10
93 INSELC
2
DATA 11
INSELB
3
92
CLK 12
INSELA
13
AV2TRH
14
ACTL1
15
FLYRECH
VMUTEH
IC3005
94 2
DATA
3
CLK
TRICK(H)
WF6
IC3006
98
I2C_DATA_A/V
I2C_CLK_A/V
IC3007
4
NRECL
5
VHSH
7
L1INF_A/AV1
9
95 2
L1INF_B
DATA
8
3
L2INF0/RGB
CLK
12
VUP2L REG.
13
CONTROL
VUPH
14
P.CTLH Q3006-Q3010
15
P.SAVEL
IC3003
( SERIAL MEMORY )
5
SDA
6
SCL
76
75
E F
29/11/2016
CN3008
REC_SAFETY
3
4 S_CLK
TO DISPLAY
S_DATA_TOSYS
5
CN7002
6 S_DATA_FRSYS
10 D_CASS_SW
I2C_DATA_A/V
I2C_CLK_A/V
TO
D_VHS(L)
VIDEO/AUDIO
FLY_REC(H)
N.REC(L)
VHS(H)
CN3011
HS_RECST(H)
14
A/HS2.FF
13
HS2_ENV
12
D_REC_LEVEL2
11
D_REC_LEVEL1
8
TO DIGITAL
D/HS1_ENV
7
(PRE/REC)
V/STD/HS1.FF
6
CN605
CH1_RECST(H)
5
CH2_RECST(H)
4
D_REC(L)
3
2 D_VHS(L)
HS(H)
1
A.IN_SEL_C
A.IN_SEL_B
TO
A.IN_SEL_A
AUDIO I/O
AV2THROUGH(L)
AUDIO_CTL1
6 TO
YU_V_MUTE(H)
TUNER
12
CN7104
16 TRICK(H)
C.SYNC/V.REF TO 3D DIGITAL/4M
14
I2C_DATA_A/V CN1401
12
I2C_CLK_A/V
11
CN7103
I2C_DATA_A/V TO S-SUB
2
3 I2C_CLK_A/V CN511
CN7105
TO TERMINAL
LINE1INF0/I2C_DATA2
13
CN7102
LINE2INF0/I2C_CLK2
14
CN5601
4 P.CTL(H) TO SUB REG
P.SAVE(L)
3 CN5503
I2C_CLK2
I2C_DATA2
TO
I2C_DATA2
SYNC-DET/PDC
I2C_CLK2
G H