Mn102L62Glh (Ic401) : Unit Cpu - JVC XV-S300BK Service Manual

XV-S300BK/XV-S332SL/XV-S402SL/XV-S403SG

4.11MN102L62GLH (IC401) : Unit CPU

4.11.1 Pin function
Pin No. Symbol I/O
1 WAIT I Micon wait signal input
2 RE O Read enable
3 SPMUTE O Spindle muting output to IC251
4 WEN O Write enable
5 HDTYPE O HD Type selection
6 CS1 O Chip select for ODC
7 CS2 O Chip select for ZIVA
8 CS3 O Chip select for outer ROM
9 DRVMUTE O Driver mute
10 SBRK O Short brake terminal
11 LSIRST O LSI reset
12 WORD I Bus selection input
13 A0 O Address bus 0 for CPU
14 A1 O Address bus 1 for CPU
15 A2 O Address bus 2 for CPU
16 A3 O Address bus 3 for CPU
17 VDD - Power supply
18 SYSCLK - Non connect
19 VSS - Ground
20 XI - Not use (Connect to vss)
21 XO - Non connect
22 VDD - Power supply
23 OSCI I Clock signal input(13.5MHz)
24 OSCO O Clock signal output(13.5MHz)
25 MODE I CPU Mode selection input
26 A4 O Address bus 4 for CPU
27 A5 O Address bus 5 for CPU
28 A6 O Address bus 6 for CPU
29 A7 O Address bus 7 for CPU
30 A8 O Address bus 8 for CPU
31 A9 O Address bus 9 for CPU
32 A10 O Address bus 10 for CPU
33 A11 O Address bus 11 for CPU
34 VDD - Power supply
35 A12 O Address bus 12 for CPU
36 A13 O Address bus 13 for CPU
37 A14 O Address bus 14 for CPU
38 A15 O Address bus 15 for CPU
39 A16 O Address bus 16 for CPU
40 A17 O Address bus 17 for CPU
41 A18 O Address bus 18 for CPU
42 A19 O Address bus 19 for CPU
-
43 VSS Ground
44 A20 O Address bus 20 for CPU
45 TXSEL O TX Select
46 TRVSW I Detection switch of traverse
inside
47 HUGUP - Connect to TP408
48 HFMON O HFM Control output to Q103
49 HAGUP O Connect to pick-up
50 - - Connect to TP407
34
Function Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol I/O
- - Connect to TP406
- - Connect to TP405
P85/TM5IO - Connect to TP404
VDD - Power supply
- - Connect to TP403
FEPEN O Serial enable signal for FEP
SLEEP O Standby signal for FEP
- - Connect to TP402
BUSY I Communication busy
REQ O Communication request
VSS - Ground
EPCS O EEPROM chip select
EPSK O EEPROM clock
EPDI I EEPROM data input
EPDO O EEPROM data output
VDD - Power supply
SCLKO O Communication clock
S2UDT I Communication input data
U2SDT O Communication output data
CPSCK O Clock for ADSC serial
P74/SBI1 I Not use (Pull down)
SDOUT O ADSC serial data output
- I Not use (Pull up)
- I Not use (Pull up)
NMI I NMI Terminal
ADSCIRQ I Interrupt input of ADSC
ODCIRQ I Interrupt input of ODC
DECIRQ I Interrupt input of ZIVA
CSSIRQ I Not use (Pull down)
ODCIRQ2 I Interruption of system control
ADSEP I Address data selection input
RST I Reset input
VDD - Power supply
TEST1 I Test signal 1 input
TEST2 I Test signal 2 input
TEST3 I Test signal 3 input
TEST4 I Test signal 4 input
TEST5 I Test signal 5 input
TEST6 I Test signal 6 input
TEST7 I Test signal 7 input
TEST8 I Test signal 8 input
VSS - Ground
D0 I/O Data bus 0 of CPU
D1 I/O Data bus 1 of CPU
D2 I/O Data bus 2 of CPU
D3 I/O Data bus 3 of CPU
D4 I/O Data bus 4 of CPU
D5 I/O Data bus 5 of CPU
D6 I/O Data bus 6 of CPU
D7 I/O Data bus 7 of CPU
Function