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11.4.1
Line Control Register 0 (SILCR0)
Line Control Register 1 (SILCR1)
These registers specify the format of asynchronous transmission/reception data.
31
15
14
13
12
RWUB TWUB UODE
R/W
R/W
R/W
0
1
0
Bits
Mnemonic
Field Name
⎯
31:16
Reserved
15
RWUB
Receive Wake
Up Bit
14
TWUB
Transmit Wake
Up Bit
13
UODE
Open Drain
Enable
⎯
12:7
Reserved
6:5
SCS
Clock Select
4
UEPS
Even Parity
Select
Parity Check
3
UPEN
Enable
2
USBL
Stop Bit Length
1:0
UMODE
Mode
0xF300 (Ch. 0)
0xF400 (Ch. 1)
0
7
6
0
SCS
R/W
Wake Up Bit for Receive (Initial value: 0, R/W)
When in the Multi-Controller System mode, this field selects whether to receive
address (ID) frames whose Wake Up bits (WUB) are "1" or to receive data frames
whose Wake Up bits (WUB) are "0". This value is undefined when not in the Multi-
Controller System mode.
0: Receive data frames.
1: Receive address (ID) frames.
Wake Up Bit for Transmit (Initial value: 1, R/W)
When in the Multi-Controller System mode, this field specifies the Wake Up bit (WUB).
This value is undefined when not in the Multi-Controller System mode.
0: Data frame transfer (WUB = 0)
1: Address (ID) frame transfer (WUB = 1)
TXD Open Drain Enable (Initial value: 0, R/W)
This field selects the output mode of the TXD signal. When in the Multi-Controller
System mode, the Slave Controller must set the TXD signal to Open Drain.
0: Totem pole output
1: Open drain output
SIO Clock Select (Initial value: 10, R/W)
This field selects the serial transfer clock. The clock frequency that is the serial
transfer clock divided by 16 becomes the baud rate (bps).
00: Internal clock (IMBUSCLKF)
01: Baud rate generator output that divided IMBUSCLKF
10: External clock (SCLK)
11: Baud rate generator output that divided SCLK
UART Even Parity Select (Initial value: 0, R/W)
This field selects the parity mode.
0: Odd parity
1: Even parity
UART Parity Enable (Initial value: 0, R/W)
This field selects whether to perform the parity check.
0: Disable the parity check
1: Enable the parity check
UART Stop Bit Length (Initial value: 0, R/W)
This field specifies the stop bit length.
0: 1 bit
1: 2 bits
UART Mode (Initial value: 00, R/W)
This field sets the data frame mode.
00: 8-bit data length
01: 7-bit data length
10: Multi-Controller 8-bit data length
11: Multi-Controller 7-bit data length
Figure 11.4.1 Line Control Register
11-14
Chapter 11 Serial I/O Port
5
4
3
2
UEPS UPEN USBL
R/W
R/W
R/W
10
0
0
0
Description
⎯
⎯
16
: Type
: Initial value
1
0
UMODE
R/W
: Type
00
: Initial value
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