Yamaha MCX-A10 Service Manual page 31

Pin No. Symbol
109 TX25
118 RX25
121-124 RXD0-RXD3
25 MDI Management Data Input
26 MDO Management Data Output
27 MCLK
126 RX_ER
2 nCSOUT
12 RBIAS
14 TPO+
15 TPO-
17 TPI+
18 TPI-
22 nLEDA
23 nLEDB
SIGNAL DESCRIPTION PARAMETERS
Presence of "n" at the beginning of a signal indicates that the signal is in the active low state and its absence indicates the active high state of the signal.
"assert" or "assertion" indicates that the signal is effective regardless whether the voltage level is high or low. "negata" or "negation" indicates that the signal
is ineffective. Also, "high-Z" indicates that the signal is in the tri-state.
"Undefined" means that the signal can be high, low, tri-state or intermediate level.
Buffer Types
O4 Output buffer with 2mA transmission side and 4mA reception side
O12 Output buffer with 6mA transmission side and 12mA reception side
O16 Output buffer with 8mA transmission side and 16mA reception side
O24 Output buffer with 12mA transmission side and 24mA reception side
OD16 Open drain buffer with 16mA reception side
I/O4 Bidirectional buffer with 2mA transmission side and 4mA reception side
I/O24 Bidirectional buffer with 12mA transmission side and 24mA reception side
I/OD Bidirectional open drain buffer with 4mA reception side
I Input buffer
IS Input buffer with Schmidt trigger hysteresis
Iclk Clock input buffer
I/O Difference input
O/I Difference output
** 5V traylant
Name Buffer Type
Transmit Clock I with pullup **
Receive Clock I with pullup **
Receive Data I with pullup **
I with pulldown **
Management Clock
Receive Error I with pulldown **
nChip Select Output
External Register NA
OD16
OD16
Input signal. The clock input from MII is transmitted. 4 bit rate
clock (25 MHz for 100 Mbps and 2.5 Mbps for 10 Mbps)
Input signal. The clock input from MII PHY is received. 4 bit
rate clock (25 MHz for 100 Mbps and 2.5 Mbps for 10 Mbps)
Input signal. 4 bits of the receiving data from MII PHY.
MII management data input signal.
O4 MII management data output signal.
O4 MII management clock.
This pin is for the input signal which indicates an error of the
code detected by PHY. It is used to remove the bucket being
received by LAN91C111. The error reported by this event has
the same meaning as a faulty CRC. (Receive Status Word 13)
O4 This pin is for the output signal. Chip select is provided for
mapping to the space of LAN91C111 with PHY function. It
enables accessing the 8-bit lower address of LAN91C111
when BANK SELECTED is "7".
This pen is for setting the transmission current. The output
current for TP transmission output is set by the external re-
sistor connected between this pin and GND.
O/I This pin is for output signal to transmit positive twist pair.
O/I This pin is for output signal to transmit negative twist pair.
I/O This pin is for output signal to receive positive twist pair.
I/O This pin is for input signal too receive negative twist pair.
This pin is for PHY LED output.
This pin is for PHY LED output.
MCX-A10/MCX-SP10
Function
31