Casio CZ-1 Service Manual And Spare Parts List page 79

7.
CPU 0iPD7810H)
As
CPU
(mPD7810H)
does not nava
a
in tar
ml ROM,
it
accesses control data for
system
execusion
from a external
ROM
directly.
Main
CPU
and
Sub
CPU
have different functions.
7-1.
Pin Functions of
Main
CPU
Pin No.
Tt
rminal
Namt
In/Out Function
1-8
PAO(SO)
-
PA7(S7)
In/Out Data but for
LCD
end
RAM
pack. Signal
PA0~PA3
also
ganarata
kay
common
signal.
9
PBO
(SYC) In
Synchronous
signal
from
CPU
intartaca
LSI
vMBo4ni73l.
11
PB2
(INT)
Out
Sub
CPU
intarrupt signal.
12
PB3 (CONT) In/Out Control signal
batwtan Main and Sub CPUs.
13
PB4
(RCE)
Out
Chip
tnabla signal for
HAM
pack.
14
PBS
(RS)
Out Control signal for
LCO
unit.
15
PB6
(R/W)
Out Rtad/Writa signal for
RAM
pack and
LCD
unit.
16
PB7
(LE)
Out Enablt
signal for
LCO
unit.
17
PCO (TXD) Out
MIDI
(Musical
Instrumtnt Digital Intarfaca) data output.
18 PC1
(RXD)
In
MIOI
data Input.
19
PC2 (SCK) In
MIOI dock pul»
input.
20
PC3
(INT49) In
Intarrupt
signal
from Kay
intarfaca LSI (jf
08049HC).
21
PC4 (CNT49)
Out
Control
signal
of
Kay
intarfaca LSI
(MPD8049HC).
22 PC6
(CI) In
Timing
signal
of data transmission
batwtan Main
CPU
and
Kay
touch control
LSI
(MSM6200).
24 PC7
(TST)
Out Chack
signal for intarnal
ROM/RAM
of
Kay
intarfaca LSI (J1PD8049HC)
at
powar ON.
26
INT1 (X896) In Intarrupt
signal
from Sub CPU.
28
RESET
In Rasat signal input.
CPU
intarnal circuits ara
initializad
whan
tha tarminal rtcaivts a
LOW
(aval
pulsa
at
powar ON.
31
XI
In
15MH1
clock pulsa input.
32 Vss
Ground
(OV)
sourca.
33
AVu
Ground
(0V) souroa
for intarnal
ADC
(Analog
to Digital
Convtrttr)
34
AN0
In
Modulation whaal
input.
Voltaga
(aval
from modulation whaal
is
oonvtrttd into
digital
data
by
built-in
AOC.
38
AN1
In Pitch
bandar whaal
input.
Voltaga
laval
from
pitch
bandar whaal
is
convtrted
into digital
data by
built-in
ADC.
36
AN2
In
Af
tar
touch
sansor input.
Voltaga
laval
from
af tar
touch
sansor
is
convartad into
digital
data
by
built-in
ADC.
42
VAREF
Rafaranea voltaga (+6V) for
built-in
ADCs.
43 AVce +5V
powar
souroa for built-in
ADCs.
44
PD
Out
Raad
signal output.
Drops
to
LOW
whan
Main
CPU
raadt data
from
paripharal davictt.
-18-