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DVDR3375 Main Board Electrical Diagram : TERM AT E5 & DDR & VREF/VT
A
TERMINATION AT E5.1
E5_SDRAM_DQ[31..0]
SDRAM_DQ[31..0]
RP20 51/RP
E5_SDRAM_DQ3
8
1
SDRAM_DQ3
E5_SDRAM_DQ1
SDRAM_DQ1
7
2
E5_SDRAM_DQ2
SDRAM_DQ2
6
3
E5_SDRAM_DQ0
5
4
SDRAM_DQ0
RP26 51/RP
E5_SDRAM_DQ4
1
8
SDRAM_DQ4
E5_SDRAM_DQ5
SDRAM_DQ5
2
7
E5_SDRAM_DQ6
SDRAM_DQ6
3
6
E5_SDRAM_DQ7
4
5
SDRAM_DQ7
RP28 51/RP
E5_SDRAM_DQ8
8
1
SDRAM_DQ8
E5_SDRAM_DQ9
SDRAM_DQ9
7
2
E5_SDRAM_DQ10
SDRAM_DQ10
6
3
E5_SDRAM_DQ11
5
4
SDRAM_DQ11
RP21 51/RP
B
E5_SDRAM_DQ12
8
1
SDRAM_DQ12
E5_SDRAM_DQ13
SDRAM_DQ13
7
2
E5_SDRAM_DQ14
SDRAM_DQ14
6
3
E5_SDRAM_DQ15
5
4
SDRAM_DQ15
RP22 51/RP
E5_SDRAM_DQ16
8
1
SDRAM_DQ16
E5_SDRAM_DQ17
SDRAM_DQ17
7
2
E5_SDRAM_DQ18
SDRAM_DQ18
6
3
E5_SDRAM_DQ19
5
4
SDRAM_DQ19
RP23 51/RP
E5_SDRAM_DQ20
1
8
SDRAM_DQ20
E5_SDRAM_DQ21
SDRAM_DQ21
2
7
E5_SDRAM_DQ22
SDRAM_DQ22
3
6
E5_SDRAM_DQ23
4
5
SDRAM_DQ23
RP24 51/RP
E5_SDRAM_DQ24
5
4
SDRAM_DQ24
E5_SDRAM_DQ25
SDRAM_DQ25
6
3
E5_SDRAM_DQ26
SDRAM_DQ26
7
2
E5_SDRAM_DQ27
8
1
SDRAM_DQ27
RP32 51/RP
E5_SDRAM_DQ31
1
8
SDRAM_DQ31
E5_SDRAM_DQ29
SDRAM_DQ29
2
7
E5_SDRAM_DQ30
SDRAM_DQ30
C
3
6
E5_SDRAM_DQ28
4
5
SDRAM_DQ28
RP35 22/RP
E5_SDRAM_DQM0
SDRAM_DQM0
1
8
E5_SDRAM_DQM1
SDRAM_DQM1
2
7
E5_SDRAM_DQM2
3
6
SDRAM_DQM2
E5_SDRAM_DQM3
SDRAM_DQM3
4
5
RP47 22/RP
E5_SDRAM_A1
8
1
SDRAM_A1
E5_SDRAM_A6
SDRAM_A6
7
2
E5_SDRAM_A3
SDRAM_A3
6
3
E5_SDRAM_A15
5
4
SDRAM_A15
RP43 22/RP
E5_SDRAM_A8
1
8
SDRAM_A8
E5_SDRAM_A0
SDRAM_A0
2
7
E5_SDRAM_A4
SDRAM_A4
3
6
E5_SDRAM_A2
4
5
SDRAM_A2
RP44 22/RP
E5_SDRAM_A7
8
1
SDRAM_A7
E5_SDRAM_A14
SDRAM_A14
7
2
D
E5_SDRAM_A9
SDRAM_A9
6
3
E5_SDRAM_A12
5
4
SDRAM_A12
RP45 22/RP
1
8
E5_SDRAM_A11
SDRAM_A11
2
7
E5_SDRAM_A10
SDRAM_A10
3
6
E5_SDRAM_A5
4
5
SDRAM_A5
E5_SDRAM_DQS0
R5
51
SDRAM_DQS0
E5_SDRAM_DQS1
R6
51
SDRAM_DQS1
E5_SDRAM_DQS2
R8
51
SDRAM_DQS2
E5_SDRAM_DQS3
R10
51
SDRAM_DQS3
E5_SDRAM_CLK0
R13
22
SDRAM_CLK0
E5_SDRAM_CLK1
R14
22
SDRAM_CLK1
E5_SDRAM_CLK#0
R16
22
SDRAM_CLK#0
E5_SDRAM_CLK#1
R18
22
SDRAM_CLK#1
RP48
22/RP
E5_SDRAM_RAS#
SDRAM_RAS#
1
8
E5_SDRAM_CLKE
2
7
SDRAM_CLKE
E5_SDRAM_CAS#
SDRAM_CAS#
3
6
E
E5_SDRAM_WE#
SDRAM_WE#
4
5
E5_SDRAM_CS0
R27
22
SDRAM_CS0
F
1
2
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3
4
The VTT side of the terminaton resistors should be placed
on a wide VTT island on the surface layer. The island is
located at each end of the bus, so it does not interfere
SSTL2_VDD
with the signal routing.
C111
C112
C290
C291
0.1UF
0.1UF
0.01UF
0.01UF
C115
C116
C292
0.1UF
0.1UF
0.01UF
SSTL2_VDD
C119
C120
C294
C295
C296
C297
0.1UF
0.1UF
0.01UF
0.01UF
0.1UF
0.1UF
C123
C124
C300
C301
C302
C303
0.1UF
0.1UF
0.01UF
0.01UF
0.1UF
0.1UF
SSTL2_VDD
C279
C280
C281
C282
C129
C130
C319
C320
C321
C283
0.1UF
0.1UF
0.01UF
0.01UF
0.1UF
0.1UF
1000PF
1000PF
1000PF
0.1UF
C284
C285
C286
C287
C135
C136
C324
C325
C326
C288
0.1UF
0.1UF
0.01UF
0.01UF
0.1UF
0.1UF
1000PF
1000PF
1000PF
0.1UF
DDR TERMINATION VOLTAGE REGULATOR
VREF needs to be decoupled
to both SSTL2_VDD and SSTL2_GND with balanced
decoupling capacitors.
VREF should be routed over a
reference plane and isolated, and possibly
shielded with both SSTL2_VDD and SSTL2_GND
U26
1
NC
VTT
2
GND
PVIN
3
VSENSE
AVIN
VREF
4
VREF
VREF
VDDQ
LP2995
C128
GND_SSTL2
0.1UF
3
4
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5
TERMINATION AT DDR
SDRAM_DQ[31..0]
VREF
VREF
GND_SSTL2
VTT
VTT
GND_SSTL2
SSTL2_VDD
C133
C322
C323
0.1UF
1000PF
1000PF
VTT
VTT
VREF
VREF
C139
C327
C328
0.1UF
1000PF
1000PF
GND_SSTL2
GND_SSTL2
VTT
CA28
C298
C127
C299
C329
+
+
+
220UF/10V
10UF/6V/A
0.1UF
10UF/6V/A
0.1UF
8
7
SSTL2_VDD
6
5
C315
+
CA29
220UF/10V
0.1UF
5
6-10
6
7
VTT
RP7 51/RP
SDRAM_DQ0
8
1
SDRAM_DQ1
7
2
SDRAM_DQ2
6
3
SDRAM_DQ3
5
4
RP9
51/RP
SDRAM_DQ4
8
1
SDRAM_DQ5
7
2
SDRAM_DQ6
6
3
SDRAM_DQ7
5
4
RP11 51/RP
SDRAM_DQ8
4
5
SDRAM_DQ9
3
6
SDRAM_DQ10
2
7
SDRAM_DQ11
1
8
RP13 51/RP
SDRAM_DQ12
4
5
SDRAM_DQ13
3
6
SDRAM_DQ14
2
7
SDRAM_DQ15
1
8
RP19 51/RP
SDRAM_DQ16
8
1
SDRAM_DQ17
7
2
SDRAM_DQ18
6
3
SDRAM_DQ19
5
4
RP15 51/RP
SDRAM_DQ20
8
1
SDRAM_DQ21
7
2
SDRAM_DQ22
6
3
SDRAM_DQ23
5
4
RP17
51/RP
SDRAM_DQ24
8
1
SDRAM_DQ25
7
2
SDRAM_DQ26
6
3
SDRAM_DQ27
5
4
RP18
51/RP
SDRAM_DQ28
8
1
SDRAM_DQ29
7
2
SDRAM_DQ30
6
3
SDRAM_DQ31
5
4
RP8
51/RP
SDRAM_A0
8
1
SDRAM_A1
7
2
SDRAM_A2
6
3
SDRAM_A3
5
4
RP10 51/RP
SDRAM_A7
1
8
SDRAM_A6
2
7
SDRAM_A5
3
6
SDRAM_A4
4
5
RP12
51/RP
SDRAM_A12
1
8
SDRAM_A11
2
7
SDRAM_A9
3
6
SDRAM_A8
4
5
RP14 51/RP
SDRAM_RAS#
8
1
SDRAM_A14
7
2
SDRAM_A15
6
3
SDRAM_A10
5
4
SDRAM_DQS0
R162
51
SDRAM_DQS1
R164
51
SDRAM_DQS2
R11
51
SDRAM_DQS3
R168
51
SDRAM_DQM0
R15
51
SDRAM_DQM1
R17
51
SDRAM_DQM2
R19
51
SDRAM_DQM3
R20
51
SDRAM_CLK#0
R21
51
SDRAM_CLK#1
R22
51
SDRAM_CLK0
R23
51
SDRAM_CLK1
R24
51
SDRAM_CLKE
R442
51
SDRAM_WE#
R443
51
SDRAM_CAS#
R444
51
SDRAM_CS0
R31
51
6
7
8
A
C111
A3
C112
A3
C115
B3
C116
B3
C119
B3
C115
B3
C120
B3
C123
C3
C124
C3
C127
E5
C128
E4
C129
C3
C130
C3
C135
C3
C136
C3
C139
D5
C279
C2
C280
C3
C281
C3
C282
C3
B
C283
C4
C284
C3
C285
D3
C286
D3
C287
D3
C287
D4
C290
B4
C291
B4
C292
B4
C294
B4
C295
B4
C296
B4
C297
B4
C298
E5
C299
E5
C300
B4
C301
C4
C302
C4
C303
C4
C315
E5
C319
C4
C320
C4
C321
C4
C322
C5
C323
C5
C324
D4
C325
D4
C
C326
D4
C327
D5
C328
D5
C329
E5
CA28
E5
CA29
E5
R10
E1
R11
D6
R13
E1
R14
E1
R15
E6
R16
E1
R162
E6
R164
E6
R168
E6
R17
E6
R18
E1
R19
E7
R20
E7
R21
E7
R22
E7
R23
E7
R24
E7
R27
E1
R31
E7
R442
E7
R443
E7
D
R444
E7
R5
E1
R6
E1
R8
E1
RP10
D7
RP11
B7
RP12
D7
RP13
B7
RP14
D7
RP15
C7
RP16
C7
RP17
C7
RP18
C7
RP19
C7
RP20
A1
RP21
B1
RP22
B1
RP23
B1
RP24
C1
RP26
B1
RP28
B1
RP32
C1
RP35
C1
RP43
D1
RP44
D1
RP45
D1
RP47
D1
E
RP48
E1
RP7
B7
RP8
D7
RP9
B7
U26
E4
F
8
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