Table Of Contents - Yamaha Mio Service Manual

Table of Contents

Table Of Contents2
Schematic Diagram3
Steel Rodent Technologies5
74Ls20 Dual 4-Input Nand Gate10
Pin Connections (Top View)10
Truth Table10
Iec Logic Symbol10
U2, U12, U24 74Ls175 Quad D Flip-Flop11
Connection Diagram Tip (Top View)11
Pin Names11
Logic Diagram11
Functional Description12
U3, U4 74Ls138 3-To-8 Line Decoder13
Pin Assignment For Dip, Soic, Sop And Tssop Data Outputs13
U57407 Hex Buffer/Driver15
U6 6551 Asynchronous Communication Interface Adapter (Acia)16
Features16
Description16
Block Diagram16
Write Cycle17
Crystal Specifications17
Clock Generation17
Write Timing Characteristics17
Read Cycle18
Read Timing Characteristics18
Transmit/Receive Characteristics19
Interface Signal Description19
Acia/Modern Interface Signal Description20
Internal Organization20
Control Register21
Command Register22
Status Register22
Transmit And Receive Data Registers22
U7, U10 74Ls04 Hex Inverter23
U8 74Ls02 Quad 2-Input Nor Gate24
U9, U25 74Ls93 4-Bit Binary Counter25
Connection Diagram Dip (Top View)25
U11 74Ls10 Triple 3-Input Nand Gate28
U13, U21, U67, U69 74Ls00 Quad 2-Input Nand Gate29
U14, U26, U29, U49, U68 74Ls244 Octal Buffer/Line Driver With Tri-State Outputs30
U15 27C128 16K X 8 Eprom31
U16, U20 74Ls73A Dual J-K Flip-Flop With Clear32
U17 Mc1489P Quad Line Receiver35
U18 Lm3086 Transistor Array36
U19 74Hc4046 Phase Locked Loop37
Logic Diagram For Vco39
Phase Comparators39
Typical Phase Comparator I Waveforms40
Phase Comparator State Diagrams41
Pll State Tables41
Logic Diagram For Phase Comparator Ii42
Typical Phase Comparator Ii Output Waveforms42
Detailed Circuit Description43
U22 74Ls139 Dual 1-Of-4 Decoder/Demultiplexer44
U23 74Ls158 Quad 2-Input Multiplexer46
U27, U48 74Ls374 Octal D-Type Flip-Flop; Positive Edge Trigger; Tri-State48
U28 74Ls240 Octal Biffer/Line Driver With 3-State Outputs50
U47 Mdp1603-330G And U50 Mdp1605 221/331G Dip Package Resistor Networks51
Technical Specifications52
Mechanical Specifications52
Impedance Codes53
Circuit Applications53
Mio Dram Timing54
Understanding The Dram Timing Diagram55
Reading Data From Memory56
Simplified Read Cycle56
Writing Data To Memory57
Simplified Write Cycle57
Refreshing The Memory58
Using Cas Before Ras Refresh (Cbr)58
Using Ras Only Refresh (Ror)58
Self Refresh (Sr)58
Hardware Description59
Acia Operation59
Sasi/Scsi Interface59
Printer Interface59
Mio Register Selection60
Acia Command Register61
Acia Control Register62
Addressing The Ram63
Checking Irq Status63
Accessing The Rom63
Software Description64
Mio Configuration Parameters64
Mio Operating Variables65
Rs-232 Handler Functions And Tables66
Opening The Rs-232 Port66
Closing The Rs-232 Port66
Input Character Or Line From The Rs-232 Port67
Output Character Or Line To The Rs-232 Port67
Reading The Port Status67
Meaning Of Error Bits From Location 74668
Forcing Early Transmission Of Output Blocks68
Meaning Of Status Bits From Location 74768
Controlling Outgoing Lines Dtr, Rts, And Xmt68
Control Values Added To Aux1 (Xio 34)69
Setting Baud Rate, Stop Bits, And Ready Checking69
Codes To Add To Aux1 (Xio 36)69
Setting Translation Modes And Parity69
Control Values Added To Aux1 (Xio 38)70
Setting Concurrent Mode70
Standard Printer & Modem Cables71
Dte Serial Printer Cable Connections72
Null Modem Cable Connections72
Directly Compatable Scsi / Sasi Devices73