Ic Block Diagram - Sanyo LCD-DP55441 Service Manual

5.IC block diagram

5-1. Renesas , R8J66977BG-RFJZ
Model - SubModel
R8J66977BG-RFJZ
Features
Main CPU
32bit RISC Super-H architecture SH3 CPU core
Demodulator
ATSC A/53 compliant 8VSB receiver /w QAM.
IF AGC control interface x1ch
System decoder (Stream demultiplexer)
Video and audio ES stream filtering x1
Section filtering: max. 32 PIDs
MPEG video decoder
Single ISO-13818-2 MP@ML or MP@HL support
Supports decoding of all ATSC-compliant formats
JPEG decoder
Decode Base-line JPEG file
2D Graphics
CEA-608/CEA-708-B closed caption support
Display processor, Video input/output
Full 10bit processing
MPEG Noise Filter (De-blocking/De-ringing)
Over Drive (Panel resolution : up to WXGA)
Inputs : CVBS x3, Y/C x2, YPbPr x2, RGB x1, HDMI x3
Outputs : 10-bit dual LVDS
Audio decoder, Audio input/output
ATSC A/52 Clear QAM compliant audio decoding support
Sound Demodulator
Inputs : SIF x1, Stereo x6
Outputs : PCM (I2S) x2, S/PDIF x1, Stereo x1
Peripheral interfaces
UART x1, Legacy serial interface x2, USB High Speed x1
General purpose I/Os
Memory interfaces
Serial Flash
16b width DDR2 800Mbps(5-5-5) SDRAM x 1
Power, clock and package
1.26(±0.06)V, 1.82(±0.08)V, 3.3(±0.15)V
25MHz X'tal
376pin PBGA
Surround
Simple surround
Maximum panel size
FullHD
(1920 x 1080)
18
Number of HDMI ports
3