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CD-E500
CD-E55/E44
IC401 VHiLC78646E-1: Servo/Signal Control (LC78646E)
SLCO
SLCIST
EFMIN
RF
RFVDD
RFVSS
FIN1
FIN2
TIN1
10
TIN2
11
VREF
12
REF1
13
FE
14
TEC
TE
15
RFMON
16
JITTC
17
18
ADAVDD
ADAVSS
19
TDO
20
80
79
78
77
76
75 74
73
1
2
3
4
5
6
7
8
9
21
22
23
24
25
26 27
28
–
FIN1
+
MIX
+
–
–
FIN2
+
LPF
+
TIN1
+
TBAL
–
–
–
TIN2
TBAL
+
LEVEL SET
REF1
RAM
DEFECT
SERVO PROCESSOR
A/D
ADIN
ADAVDD
ADAVSS
JITTER
JITTC
DETECT
SLCO
SLICE LEVEL
EFMIN
CONTROL
SLCIST
PCK
PDO1
PDO2
PLL
FR
PCKIST
VCEC
VVDD
CLV,CAV
VVSS
CONTROL
SBCK/FG
XIN
XOUT
CLOCK
16MOUT
GENERATOR
XVDD
XVSS
*RES
*WRQ
CORRECTION
CL
COMMAND
CE
INTERFACE
DI
DO
VDD5V
GENERAL-PURPOSE
CONT1, 2, 3
INTERPOLATION
CONT4, 5,
PORTS
SBCK/CONT6
8FS
ATTENUATION
DIGITAL FILTER
1bit DAC
TEST
Figure 46 BLOCK DIAGRAM OF IC
72 71
70
69 68
67
66 65
64
63 62
LC78646E
29 30
31
32 33
34
35 36
37
38 39
RFVDD
RFVSS
EQ
AGC
PH
BH
LPF
SW
+
–
LPF
+
+
–
–
MNI
–
RFMON
+
CONT
VREF
TRACK JUMP
LDD
APC
LDS
AUTO ADJUST
FD0
SW
D/A
TD0
S/H
SLD0
SPD0
DRF
GPDAC
DRF
VDD5V
RUPTURE DEFECT
FRAME SYNC
FSEQ
DETECT,PROTECT INSERT,
EFM DECODE
V/*P
SUBCODE DECODE CRC
VDD
VSS
MONITOR SIGNAL SELECTOR
MONI1~5
RAM
ERROR
FSX/16MIN
AUDIO CD
C2F
EFLG
C1-2,C2-2
AUDIO OUT
DOUT
LRSY
SERIAL
MUTE
DATACK
OUT
DATA
DEEMPHSIS
ASLRCK
EXTERNAL
ASDACK
LPF
AUDIO IN
ASDFIN
– 46 –
61
60
DATA
59
DATACK
58
LRSY
57
ASDFIN
56
ASDACK
55
ASLRCK
54
16MOUT
53
EFLG
52
C2F
51
XVSS
50
FSX/16MIN
49
XIN
48
XOUT
47
XVDD
46
RVDD
45
RCHO
44
RVSS
43
LVSS
42
LCHO
41
LVDD
40
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