Hyundai H-HT5115-N Service Manual
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Hyundai H-HT5115-N Service Manual

Dvd 5.1 home theatre system
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SERVICE
SERVICE MANUAL
DVD 5.1 HOME THEATRE SYSTEM
H-HT5115-N
DA918PA

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  • Page 1 SERVICE SERVICE MANUAL DVD 5.1 HOME THEATRE SYSTEM H-HT5115-N DA918PA...

  • Page 2: Table Of Contents

    CONTENTS 1. PRECAUTIONS -----------------------------------------------------------------------------------------------------------------------2 1-1 S AFETY RECAUTIONS --------------------------------------------------------------------------------------------------------- 2-3 1-2 S ERVICING RECAUTIONS --------------------------------------------------------------------------------------------------------3 1-2-1 General Serving Precautions ------------------------------------------------------------------------------------------------3 1-2-2 Insulation Checking Procedure ---------------------------------------------------------------------------------------------4 1-3 ESD P RECAUTIONS ---------------------------------------------------------------------------------------------------------------4 2. REFERENCE INFORMATION ----------------------------------------------------------------------------------------------------5 2-1 C OMPONENT ESCRIPTIONS -----------------------------------------------------------------------------------------------------5 ------------------------------------------------------------------------------------ 6-45 2-1-1 D VD Processor Ch ip MTK1389 J -------------------------------------------...

  • Page 3: Precautions

    1. PRECAUTIONS 1-1 Safety Precautions 1) Before returning an instrument to the customer, always make a safety check of the entire instrument, including, but not limited to, the following items: (1) Be sure that no built-in protective devices are defective or have been defeated during servicing. (1) Protective shields are provided to protect both the technician and the customer.

  • Page 4: Servicing Precautions

    2) Read and comply with all caution and safety related 5) Components, parts, and/or wiring that appear to notes non or inside the cabinet, or on the chassis. have overheated or that are otherwise damaged should be replaced with components, parts and/or 3) Design Alteration Warning-Do not alter of add to the wiring that...

  • Page 5: Insulation Checking Procedure

    1-2-2 Insulation Checking Procedure attachment plug and accessible conductive parts (see Disconnect the attachment plug from the AC outlet and note) should be more than 1 Megohm. turn the power ON. Connect the insulation resistance Note: Accessible conductive parts include metal meter (500V) to the blades of the attachment plug.
  • Page 6 MT1389J Version 1.0 Desktop DVD Player SOC General Datasheet Specifications are subject to change without notice Revision History Revised date Contents of revision Reason for revision Page Remarks Release Ver 1.0 2009 6 18 MEDIATEK CONFIDENTIAL, NO DISCLOSURE...
  • Page 7 Specifications are subject to change without notice Contents of Specifications Specifications Page Revision History Contents of Specification Applications Type Usage Structure Function Pin Assignment Absolute Maximum Ratings Recommend Operation Conditions Electrical Characteristics Marking on Devices Package Description Packing Description Solder-Reflow Condition Manual Solder Condition Storage Condition Other...
  • Page 8 Specifications are subject to change without notice Applications This present specifications are applied to IC MT1389J . Type MT1389J Usage Single Chip IC for DVD Player Structure 0.13um CMOS process, Silicon material, Monolithic IC, 128pin LQFP, 3.3/1.2 Dual operation voltages. MEDIATEK CONFIDENTIAL, NO DISCLOSURE...
  • Page 9 Specifications are subject to change without notice Function 5-1 General Description is a cost-effective DVD system-on-chip (SOC) which incorporates advanced features like MediaTek MT1389J MPEG-4 video decoder, high quality TV encoder and state-of-art de-interlace processing. The MT1389J enables consumer electronics manufacturers to build high quality, USB2.0, MS/SD/MMC reader, feature-rich DVD players, portable DVD players or any other home entertainment audio/video devices.
  • Page 10 Specifications are subject to change without notice 5-2 Key Features RF/Servo/MPEG Integration Embedded 6ch Audio DAC Embedded 2ch Audio ADC for Karaoke High Performance Audio Processor High Performance Progressive Video Processor Support DivX Ultra High Quality 108MHz/12-bit, 4 CH TV Encoder USB 2.0 High-Speed 5-3 Applications Standard DVD Players...
  • Page 11 Specifications are subject to change without notice 5-4 General Feature lists Super Integration DVD player single chip DVD-ROM/CD-ROM Decoding Logic High performance analog RF amplifier Servo controller and data channel processing High-speed ECC logic capable of correcting MPEG-1/MPEG-2/JPEG video one error per each P-codeword or Q-codeword Dolby AC-3/DTS Decoder Automatic sector Mode and Form detection Unified memory architecture...
  • Page 12 Specifications are subject to change without notice Key shift up to +/- 8 keys Chorus/Flanger/Harmony/Reverb Channel equalizer 3D surround processing include virtual surround and speaker separation TV Encoder Four 108MHz/12bit DACs Support NTSC, PAL-BDGHINM, PAL-60 Support 525p, 625p progressive TV format Automatically turn off unconnected channels Support Macrovision 7.1 L1, Macrovision 525P and 625P...
  • Page 13 Specifications are subject to change without notice General Feature – Third Party Proprietary Right 1. Dolby License Supply of this Implementation of Dolby technology does not convey a license nor imply a right under any patent, or any other industrial or intellectual property right of Dolby Laboratories, to use this Implementation in any finished end-user or ready-to-use final product.
  • Page 14 Specifications are subject to change without notice 5-5 Pin Definitions Abbreviations: SR: Slew Rate PU: Pull Up PD: Pull Down SMT: Schmitt Trigger 4mA~16mA: Output buffer driving strength. Main Alt. Type Description Analog Interface (62) Analog RFIP AC coupled DVD RF signal input RFIP Input Analog AC coupled DVD RF signal input RFIN...
  • Page 15 Specifications are subject to change without notice Main Alt. Type Description XTALO Output 27MHz crystal output Analog AGND33 Analog Ground Ground Analog Reference voltage 2.0V output Analog Reference voltage 1.4V output Current reference input. It generates reference current for RF path. Analog Connect an external 15K resistor to this pin and AVSS REXT...
  • Page 16 Specifications are subject to change without notice Main Alt. Type Description USB ground pin VSS33_USB Ground Analog USB generating reference current PAD_VRT Inout USB Power USB Power pin 1.2V VDD12_USB DACVDDC Power 3.3V power pin for video DAC circuitry Bandgap reference voltage VREF GPO14 Analog...
  • Page 17 Specifications are subject to change without notice Main Alt. Type Description AUDIO DAC left channel output Analog TXD2 GPIO1 ASDATA1 Output GPIO_AL AUDIO DAC LS channel output Analog ALRCK GPIO Output GPIO_ALS AUDIO DAC CENTER channel output Analog Audio Mute GPIO ASDATA0 /CENTER...
  • Page 18 Specifications are subject to change without notice Main Alt. Type Description InOut SF_CK 8mA, SR Serial Flash Clock PD, SMT Microcontroller port 1-6 InOut SD_D1 set D UP1_6 4mA, SR MS_D1 set D RXD3 PU, SMT C SCK Microcontroller port 1-7 InOut SD_D2 set D 4mA, SR...
  • Page 19 Specifications are subject to change without notice Main Alt. Type Description InOut DRAM data 3 InOut DRAM data 4 InOut DRAM data 5 InOut DRAM data 6 InOut DRAM data 7 InOut DQM0 Data mask 0 2mA, PD InOut RD15 DRAM data 15 InOut RD14...
  • Page 20 Specifications are subject to change without notice Main Alt. Type Description InOut DRAM address 9 2mA, PD InOut DRAM address 8 2mA, PD InOut DRAM address 7 2mA, PD InOut DRAM address 6 2mA, PD InOut DRAM address 5 2mA, PD InOut DRAM address 4 2mA, PD...
  • Page 21 Specifications are subject to change without notice Main Alt. Type Description InOut Dram Clock Enable 4mA, PD SD_CLK set A/C MS_CLK set A/C Y4/Y3 GPIO7 ACLK ASDATA1 MCDATA Microcontroller port 1-4 (Internal Pull-Up) GPIO 7 GPIO (11) SD_CLK set E SD_CMD set A/C MS_BS set A/C Y5/Y2...
  • Page 22 Specifications are subject to change without notice Main Alt. Type Description SD_D0 set G InOut MS_D0 set F GPIO29 Y3/Y4 4mA, PD GPIO29 SD_CMD set G MS_BS set F InOut GPIO30 Y2/Y5 4mA, PU AS_DATA3 GPIO30 SD_CLK set G MS_CLK set F InOut GPIO31 Y1/Y6...
  • Page 23 Specifications are subject to change without notice 5-6 Functional Block CVBS, Y/C Debug 108MHz Port Component Module TV Encoder Video RF Amplifier Video DAC Servo IO Motor Servo Video Drive Processor Processor interlacer Spindle Control FLASH MPEG-1/2/4 Audio JPEG Memory Video Decoder Controller Internal...
  • Page 24 Specifications are subject to change without notice Pin Assignment DACVDDC GPIO33 GPIO10 Audio Audio Video SPDIF / GPIO12 AVDD12_2 AVDD33_1 XTALI XTALO INT RF RA10 AGND33 DVDD12 REXT / GPO5 DVDD33 MDI1 LDO1 RAS# LDO2 CAS# DVSS12 AVDD33_2 RWE# TRAY_OPEN MT1389J TRAY_CLOSE FG / GPIO2...
  • Page 25 Specifications are subject to change without notice Absolute Maximum Ratings Symbol Parameters Value Unit VDD3 3.3V Supply voltage -0.3 to 3.6 VDD2 1.2V Supply voltage -0.3 to 2.1 VDDA Analog Supply voltage -0.3 to 3.6 (3.3V) Input Voltage (3.3V IO) -0.3 to 3.63 (5V-tolerance) Input Voltage (5V-tolerance IO) -0.3 to 5.5...
  • Page 26 Specifications are subject to change without notice Electrical Characteristics 9-1 DC Characteristics Symbol Parameters Unit = 2 ~ 16mA) (3.3V) Output voltage high (3.3V IO) = 2 ~ 16mA) (3.3V) Output voltage low (3.3V IO) Pull-up Resistance KΩ Pull-down Resistance KΩ...
  • Page 27 Specifications are subject to change without notice 9-3 Built-in Audio-ADC Characteristics Test Condition: DSP MIC1 Gain = 0 (0) MIC threshold=0 DSP MIC2 Gain = 0dB.(2000) Apwin output Z= 600 Echo level = 0 dB Measure SPDIF output. CIC filter right shift 3 bit Test signal : 1K Hz sin wave Vpp(V) Max Input (with output THD+N <60...
  • Page 28 Specifications are subject to change without notice 9-4 Built-in Video-DAC Specifications Input Codes for Video Application: NTSC NTSC w/setup 525_I 525_I w/setup 525_P Programable, Programable, Programable, Programable, Programable, Current setting: Current setting: Current setting: Current setting: Current setting: WHITE (235) 3297 3297 3297...
  • Page 29 Specifications are subject to change without notice Output Compliance 1.35 DAC Output Delay DAC Rise/Fall Time Voltage Reference Reference Voltage Output 1.27 Reference Input Current 2.267 Static Performance DAC Resolution Bits DNL Differential Non-Linearity +/-0.2 */-0.25 +/-0.3 INL Integral Non-Linearity +/-0.35 */-0.4 +/-0.49 Dynamic Performance Differential Gain...
  • Page 30 Specifications are subject to change without notice Item Designator Conditions Unit 05h=30; low gain MA → FEO Focusing Error Gain 10.3 11.5 With 10KHz Sin Input 05h=7C; low gain Focusing Error Frequency MA → FEO With 10KHz, 300KHz Sin Input 23.9 Response R=G(10kHz)-G(300Khz)
  • Page 31 Specifications are subject to change without notice Item Designator Conditions Unit MA → TEO Tracking Error Common 07h=7F; low gain MB → TEO Mode Gain With 10KHz Sin Input Toggle 07h bit6, 5 MA → TEO Tracking Error H/L Gain With 10KHz Sin Input Tracking Error offset Input Floating...
  • Page 32 Specifications are subject to change without notice Input Instruction Hold After PSEN high Input Instruction Float After PSEN high 1.0Tf-5 Port 0 Address to Valid Instruction 3.0Tf-20 Port 2 Address to Valid Instruction 3.5Tf-20 PSEN Low to Address Float A L E P S E N P o rt 0 A D R [7 :0 ]...
  • Page 33 Specifications are subject to change without notice XTALI YUV[7:0] YUV[7:0] YUV[7:0] HSYNC VSYNC Digital Video Output Interface Timing Diagram 9-10 SPDIF I/O Interface Parameter Symbol Units BCK negative edge to ASDATA valid ASDATA/LRCK input setup ASDATA/LRCK input hold ASDATA/LRCK ASDATA/LRCK SPLIN_BCK ASDATA/LRCK ASDATA/LRCK...
  • Page 34 Specifications are subject to change without notice 9-11 DRAM Interface tRAS tRCD Row Active Read Write Precharge Row Active Parameter Symbol Units CLK cycle time CAS latency = 3 SDRAM input setup time 1.75 1.75 SDRAM input hold time Active to Precharge command period tRAS 100K 100K...
  • Page 35 Specifications are subject to change without notice FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE (Unit: number of clock) tRAS tRCD Frequency Latency 42ns 18ns 18ns 6ns/10ns 133MHz (7.5ns) 125MHz (8ns) 100MHz (10ns) (Unit: number of clock) tRAS tRCD Frequency Latency 49ns 20ns 20ns 7ns/10ns...
  • Page 36 Specifications are subject to change without notice Marking on Devices MediaTek Logo Product Name MT1389 FE Lead Free Product Date Code (Year+Week) YYWW- JXXL LLLLL MTK Production Code Lot No. Package Description 11-1 Package Outline Dimension The bend lead are controlled under the criteria 0.075mm (2.5mil). MEDIATEK CONFIDENTIAL, NO DISCLOSURE...
  • Page 37 Specifications are subject to change without notice MEDIATEK CONFIDENTIAL, NO DISCLOSURE...
  • Page 38 Specifications are subject to change without notice 11-2 Weight of the chip 0.65g 11-3 Material and Finish of Lead Terminals For Lead-free Package, Materials of terminal is Sn(98%) and Bi (2%) and thickness is 300~600u inch, similar as SnPb. 11-4 Package Material Lead frame: Cu Epoxy: 1033BF Molding compound: G700...
  • Page 39 Specifications are subject to change without notice MEDIATEK CONFIDENTIAL, NO DISCLOSURE...
  • Page 40 Specifications are subject to change without notice 12-2 Desiccants Size: 110*120 mm. Weight: 66g 12-3 Aluminum Foil Bag Size: 250*500 mm. Thickness: 0.12 +/- 0.005 mm. Surface impedance: 10 Ohm/SQ 12-4 Box Description Material: 3 Layer B corrugated paper. Strength: 1176000 PA. Box size: 355(L)*157(W)*90.5(H) mm.
  • Page 41 Specifications are subject to change without notice 12-7 Packing Flow Pin No. 1 90pcs per tray direction Empty tray tray Label is on top of the Aluminum foil bag. Aluminum foil bag MEDIATEK CONFIDENTIAL, NO DISCLOSURE...
  • Page 42 Specifications are subject to change without notice Air cap Box with the Aluminum foil bag 6 box per carton Side plank Label is on top of the BOX. Fill with empty box if the quantity is less than 6 box MEDIATEK CONFIDENTIAL, NO DISCLOSURE...
  • Page 43 Specifications are subject to change without notice Solder-Reflow Condition 13-1 Reflow Condition MediaTek can guarantee 3 times IR reflow based on the reflow profile (Figure 1). Average ramp-up rate (Ts to peak): 3 C /sec. max. Preheat & Soak: Pb-Free 150~200 C (SnPb Eutectic 100~150 C) for 60~120 seconds Liquidous temperature maintained above Pb-Free 217...
  • Page 44 Specifications are subject to change without notice MEDIATEK CONFIDENTIAL, NO DISCLOSURE...
  • Page 45 Specifications are subject to change without notice 13-2 Pre-process and Heat Treatment Procedure: (MRT L3) [Package opening] [Baking] [Humidification] [Reflow] Conditions between each step of procedure Be lift for duration of 2 hours or longer at temperature of 30 C or lower and a humidity of 60% R.H. or lower.
  • Page 46 EN25F16 Purpose Eon Silicon Solution Inc. (hereinafter called “Eon”) is going to provide its products’ top marking on ICs with < cFeon > from January 1st, 2009, and without any change of the part number and the compositions of the ICs. Eon is still keeping the promise of quality for all the products with the same as that of Eon delivered before.
  • Page 47 EN25F16 EN25F16 16 Megabit Serial Flash Memory with 4Kbytes Uniform Sector FEATURES • Single power supply operation • Software and Hardware Write Protection: - Full voltage range: 2.7-3.6 volt - Write Protect all or portion of memory via • Serial Interface Architecture software - SPI Compatible: Mode 0 and Mode 3 - Enable/Disable protection with WP# pin...
  • Page 48 EN25F16 Figure.1 CONNECTION DIAGRAMS 8 - LEAD SOP / DIP 8 - CONTACT VDFN Figure 2. BLOCK DIAGRAM This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com or modifications due to changes in technical specifications. Rev.
  • Page 49 EN25F16 SIGNAL DESCRIPTION Serial Data Input (DI) The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be serially written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK) input pin. Serial Data Output (DO) The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from (shifted out of) the device.
  • Page 50 EN25F16 MEMORY ORGANIZATION The memory is organized as: 2,097,152 bytes Uniform Sector Architecture 32 blocks of 64-Kbyte 512 sectors of 4-Kbyte 8192 pages (256 bytes each) Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector, Block or Chip Erasable but not Page Erasable.
  • Page 51 EN25F16 0EF000h 0EFFFFh 0E0000h 0E0FFFh 0DF000h 0DFFFFh 0D0000h 0D0FFFh 0CF000h 0CFFFFh 0C0000h 0C0FFFh 0BF000h 0BFFFFh 0B0000h 0B0FFFh 0AF000h 0AFFFFh 0A0000h 0A0FFFh 09F000h 09FFFFh 090000h 090FFFh 08F000h 08FFFFh 080000h 080FFFh 07F000h 07FFFFh 070000h 070FFFh 06F000h 06FFFFh 060000h 060FFFh 05F000h 05FFFFh 050000h 050FFFh 04F000h 04FFFFh...

  • Page 52: Operating Features

    EN25F16 OPERATING FEATURES SPI Modes The EN25F16 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as shown in Figure 3, concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash.
  • Page 53 EN25F16 All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase instructions. Status Register.
  • Page 54 EN25F16 Table 3. Protected Area Sizes Sector Organization Status Register Memory Content Content Protect Areas Addresses Density(KB) Portion None None None None 000000h-1FFFFFh 2048KB Note: RFU = Reserved for future use Hold Function The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence.
  • Page 55 EN25F16 INSTRUCTIONS All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).
  • Page 56 EN25F16 Manufacturer/ (M7-M0) (ID7-ID0) dummy dummy Device ID (ID7-ID0) (M7-M0) (ID15-ID8) (ID7-ID0) Read Identification (M7-M0) Enter OTP mode Notes: 1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from the device on the DO pin.
  • Page 57 EN25F16 Figure 6. Write Disable Instruction Sequence Diagram Read Status Register (RDSR) (05h) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress.
  • Page 58 EN25F16 The status and control bits of the Status Register are as follows: WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.
  • Page 59 EN25F16 Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered. NOTE : In the OTP mode, WRSR command will ignore input data and program OTP_LOCK bit to 1. Figure 8. Write Status Register Instruction Sequence Diagram Read Data Bytes (READ) (03h) The device is first selected by driving Chip Select (CS#) Low.
  • Page 60 EN25F16 Read Data Bytes at Higher Speed (FAST_READ) (0Bh) The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (CLK).
  • Page 61 EN25F16 Page Program (PP) (02h) The Page Program (PP) instruction allows bytes to be programmed in the memory. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by driving Chip Select (CS#) Low, followed by the in- struction code, three address bytes and at least one data byte on Serial Data Input (DI).
  • Page 62 EN25F16 Sector Erase (SE) (20h) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Sector Erase (SE) instruction is entered by driving Chip Select (CS#) Low, followed by the in- struction code, and three address bytes on Serial Data Input (DI).
  • Page 63 EN25F16 Figure 13 Block Erase Instruction Sequence Diagram Chip Erase (CE) (C7h/60h) The Chip Erase (CE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
  • Page 64 EN25F16 Deep Power-down (DP) (B9h) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest con- sumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase instructions.
  • Page 65 EN25F16 the time duration of t RES1 (See AC Characteristics) the device will resume normal operation and other instructions will be accepted. The CS# pin must remain high during the t RES1 time duration. When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by driving the CS# pin low and shifting the instruction code “ABh”...
  • Page 66 EN25F16 Read Manufacturer / Device ID (90h) The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device ID instruction.
  • Page 67 EN25F16 instruction sequence is shown in Figure 19. The Read Identification (RDID) instruction is terminated by driving Chip Select High at any time during data output. When Chip Select is driven High, the device is put in the Standby Power mode. Once in the Standby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.
  • Page 68 EN25F16 Figure 20. Enter OTP Mode Power-up Timing Figure 21. Power-up Timing Table 8. Power-Up Timing and Write Inhibit Threshold Symbol Parameter Min. Max. Unit µs (min) to CS# low Time delay to Write instruction VWI (1) Write Inhibit Voltage 2 .5 Note: 1.The parameters are characterized only.
  • Page 69 EN25F16 Table 9. DC Characteristics = - 40°C to 85°C; V = 2.7-3.6V) Symbol Parameter Test Conditions Min. Max. Unit Input Leakage Current ± 2 µA Output Leakage Current ± 2 µA Standby Current CS# = V or V µA Deep Power-down Current CS# = V , V IN = V...
  • Page 70 EN25F16 Table 11.100MHz AC Characteristics = - 40°C to 85°C; V = 2.7-3.6V) Unit Symbol Parameter Serial Clock Frequency for: FAST_READ, PP, SE, BE, DP, RES, WREN, D.C. WRDI, WRSR Serial Clock Frequency for READ, RDSR, RDID D.C. Serial Clock High Time Serial Clock Low Time Serial Clock Rise Time (Slew Rate) V / ns...
  • Page 71 EN25F16 Figure 23. Serial Output Timing Figure 24. Input Timing Figure 25. Hold Timing This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com or modifications due to changes in technical specifications. Rev. F, Issue Date: 2009/03/16...
  • Page 72 EN25F16 ABSOLUTE MAXIMUM RATINGS Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability.
  • Page 73 EN25F16 Table 12. DATA RETENTION and ENDURANCE Parameter Description Test Conditions Unit 150°C Years Data Retention Time 125°C Years Erase/Program Endurance -40 to 85 °C 100k cycles Table 13. CAPACITANCE = 2.7-3.6V) Parameter Symbol Parameter Description Test Setup Unit Input Capacitance Output Capacitance Note : Sampled only, not 100% tested, at T A = 25°C and a frequency of 20MHz.
  • Page 74 EN25F16 PACKAGE MECHANICAL Figure 26. SOP 200 mil ( official name = 208 mil ) DIMENSION IN MM SYMBOL MIN. 1.75 1.975 2.20 0.05 0.15 0.25 1.70 1.825 1.95 5.15 5.275 5.40 7.70 7.90 8.10 5.15 5.275 5.40 - - - 1.27 - - - 0.35...
  • Page 75 EN25F16 Figure 27. VDFN8 ( 5x6mm ) Controlling dimensions are in millimeters (mm). DIMENSION IN MM SYMBOL MIN. 0.70 0.75 0.80 0.00 0.02 0.04 - - - 0.20 - - - 5.90 6.00 6.10 4.90 5.00 5.10 3.30 3.40 3.50 3.90 4.00 4.10...
  • Page 76 EN25F16 Figure 28. PDIP8 DIMENSION IN INCH SYMBOL MIN. - - - - - - 0.210 0.015 - - - - - - 0.125 0.130 0.135 0.355 0.365 0.400 0.300 0.310 0.320 0.245 0.250 0.255 0.115 0.130 0.150 0.310 0.350 0.375 Θ...
  • Page 77 EN25F16 ORDERING INFORMATION EN25F16 PACKAGING CONTENT (Blank) = Conventional P = RoHS compliant TEMPERATURE RANGE I = Industrial (-40°C to +85°C) PACKAGE H = 8-pin 200mil SOP W = 8-pin VDFN Q = 8-pin PDIP SPEED 100 = 100 Mhz BASE PART NUMBER EN = Eon Silicon Solution Inc.
  • Page 78 EN25F16 Revisions List Revision No Description Date Preliminary draft 2007/05/02 1. Correct the extra OTP sector from 256 bytes to 512 bytes on page 1 2008/03/10 and 22. 2. Correct the OTP sector is mapping to sector from 255 to 511 on page 3.
  • Page 79 ESMT M12L64164A Revision History Revision 1.0 (13 Dec. 2001) - Original Revision 1.1 (10 Jan. 2002) - Add -6 spec Revision 1.2 (30 Jan. 2002) - Delete Page44 PACKING DIMENSION 54-LEAD TSOP(II) SDRAM (400mil) (1:4). Revision 1.3 (26 Apr. 2002) - tRFC : 60ns.
  • Page 80 ESMT M12L64164A Revision 2.7 (19Jun. 2006) - Add BRSW mode Revision 2.8 (06 Jul. 2006) - Modify some description for BRSW. Revision 2.9 (08 Dec. 2006) - Add BGA type to ordering information Revision 3.0 (16 Mar. 2007) - Delete the mark of BGA package in packing diemension Revision 3.1 (31 Jul.

  • Page 81: Pin Assignment

    ESMT M12L64164A SDRAM 1M x 16 Bit x 4 Banks Synchronous DRAM FEATURES ORDERING INFORMATION PRODUCT NO. MAX FREQ. PACKAGE Comments JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address M12L64164A-5TG 200MHz 54 TSOP II Pb-free Four banks operation M12L64164A-6TG 166MHz 54 TSOP II...
  • Page 82 ESMT M12L64164A FUNCTIONAL BLOCK DIAGRAM Clock Generator Bank D Bank C Bank B Address Address Buffer Mode Bank A & Register Refresh Counter Sense Amplifier L(U)DQM Column Column Decoder Address Buffer & Refresh Counter Data Control Circuit PIN FUNCTION DESCRIPTION NAME INPUT FUNCTION System Clock...
  • Page 83 ESMT M12L64164A ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL VALUE UNIT Voltage on any pin relative to V -1.0 ~ 4.6 Voltage on V supply relative to V -1.0 ~ 4.6 ° Storage temperature -55 ~ +150 Power dissipation Short circuit current Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
  • Page 84 ESMT M12L64164A DC CHARACTERISTICS ° Recommended operating condition unless otherwise noted，TA = 0 to 70 VERSION PARAMETER SYMBOL TEST CONDITION UNIT NOTE ≥ t Burst Length = 1, t = 0 mA, Operating Current RC(min) (One Bank Active) tcc = tcc(min) ≤...
  • Page 85 ESMT M12L64164A AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V ，TA = 0 to 70 C ° ) PARAMETER VALUE UNIT Input levels (Vih/Vil) 2.4/0.4 Input timing measurement reference level Input rise and fall-time tr/tf = 1/1 Output timing measurement reference level Output load condition See Fig.
  • Page 86 ESMT M12L64164A AC CHARACTERISTICS (AC operating condition unless otherwise noted) PARAMATER SYMBOL UNIT NOTE CAS latency = 3 CLK cycle time 1000 1000 1000 CAS latency = 2 CAS latency = 3 CLK to valid output delay CAS latency = 2 CAS latency = 3 Output data hold time...
  • Page 87 ESMT M12L64164A SIMPLIFIED TRUTH TABLE DQM BA0 COMMAND CKEn-1 CKEn CS RAS CAS Note A10/AP A9~A0 Register Mode Register set OP CODE Auto Refresh Entry Refresh Self Refresh Exit Bank Active & Row Addr. Row Address Auto Precharge Disable Column Read &...
  • Page 88 ESMT M12L64164A MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with MRS Address BA0, BA1 A11~A10/AP Function W.B.L CAS Latency Burst Length Test Mode CAS Latency Burst Type Burst Length Type Latency Type BT = 0 BT = 1 Mode Register Set Reserved Sequential...
  • Page 89 ESMT M12L64164A BURST SEQUENCE (BURST LENGTH = 4) Initial Adrress Sequential Interleave BURST SEQUENCE (BURST LENGTH = 8) Initial Sequential Interleave Publication Date: May 2008 Elite Semiconductor Memory Technology Inc. Revision: 3.3 11/46...
  • Page 90 ESMT M12L64164A DEVICE OPERATIONS CLOCK (CLK) POWER-UP The clock input is used as the reference for all SDRAM 1.Apply power and start clock, Attempt to maintain CKE operations. All operations are synchronized to the positive = “H”, DQM = “H” and the other pins are NOP going edge of the clock.
  • Page 91 ESMT M12L64164A DEVICE OPERATIONS (Continued) BANK ACTIVATE and burst sequence. By asserting low on CS , CAS The bank activate command is used to select a random row and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial in an idle bank.
  • Page 92 ESMT M12L64164A DEVICE OPERATIONS (Continued) AUTO PRECHARGE SELF REFRESH The precharge operation can also be performed by using The self refresh is another refresh mode available in the auto precharge. The SDRAM internally generates the timing SDRAM. The self refresh is the preferred refresh mode to satisfy t and “t ”...
  • Page 93 ESMT M12L64164A COMMANDS Mode register set command WE = Low) The M12L64164A has a mode register that defines how the device operates. In this command, A0 through A11, BA0 and BA1 are the data input pins. After power on, the mode register set command must be executed to initialize the device. The mode register can be set only when all banks are in idle state.
  • Page 94 ESMT M12L64164A Write command ( CS , CAS , WE = Low, RAS = High) If the mode register is in the burst write mode, this command sets the burst start address given by the column address to begin the burst write operation. The first write data in burst can be input with this command with subsequent data on following clocks.
  • Page 95 ESMT M12L64164A Self refresh entry command ( CS , RAS , CAS , CKE = Low , WE = High) After the command execution, self refresh operation continues while CKE remains low. When CKE goes to high, the M12L64164A exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control.
  • Page 96 ESMT M12L64164A BASIC FEATURE AND FUNCTION DESCRIPTIONS 1. CLOCK Suspend 1 ) C l o c k S u s p e n d e d D u r i n g W r i t e ( B L = 4 ) 2 ) C l o c k S u s p e n d e d D u r i n g R e a d ( B L = 4 ) C L K CM D...
  • Page 97 ESMT M12L64164A 3. CAS Interrupt (I) * N o t e 1 1 ) R e a d i n t e r r u p t e d b y R e a d ( B L = 4 ) C L K C M D A D D...
  • Page 98 ESMT M12L64164A 4. CAS Interrupt (II) : Read Interrupted by Write & DQM ( a ) C L = 2 , B L = 4 C L K i ) C M D D Q M i i ) C M D D Q M H i - Z i i i ) C M D...
  • Page 99 ESMT M12L64164A ( b ) C L = 3 , B L = 4 C L K i ) C M D D Q M i i ) C M D D Q M i i i ) C M D D Q M i v ) C M D D Q M...
  • Page 100 ESMT M12L64164A 6. Precharge 1 ) N o r m a l W r i t e ( B L = 4 ) 2 ) N o r m a l R e a d ( B L = 4 ) C L K C L K C M D...
  • Page 101 ESMT M12L64164A 8. Burst Stop & Interrupted by Precharge 1 ) W r i t e B u r s t S t o p ( B L = 8 ) 1 ) W r i t e i n t e r r u p t e d b y p r e c h a r g e ( B L = 4 ) C L K C L K * N o t e 3...
  • Page 102 ESMT M12L64164A 10. Clock Suspend Exit & Power Down Exit 1 ) C l o c k S u s p e n d ( = A c t i v e P o w e r D o w n ) E x i t 2 ) P o w e r D o w n ( = P r e c h a r g e P o w e r D o w n ) C L K C L K...
  • Page 103 ESMT M12L64164A 12. About Burst Type Control At MRS A3 = “0”. See the BURST SEQUENCE TABLE. (BL = 4,8) Sequential Counting BL = 1, 2, 4, 8 and full page. Basic MODE At MRS A3 = “1”. See the BURST SEQUENCE TABLE. (BL = 4,8) Interleave Counting BL = 4, 8 At BL =1, 2 interleave Counting = Sequential Counting Every cycle Read/Write Command with random column address can realize...
  • Page 104 ESMT M12L64164A FUNCTION TURTH TABLE (TABLE 1) Current ADDR ACTION Note State ILLEGAL IDLE CA, A10/AP ILLEGAL Row (&Bank) Active ; Latch RA A10/AP Auto Refresh or Self Refresh OP code OP code Mode Register Access ILLEGAL CA, A10/AP Begin Read ; latch CA ; determine AP Active CA, A10/AP Begin Write ;...
  • Page 105 ESMT M12L64164A Current ADDR ACTION Note State Idle after tRP Read with Idle after tRP Auto ILLEGAL Precharge ILLEGAL ILLEGAL A10/AP Idle after tRPL ILLEGAL Row Active after tRCD Row Active after tRCD ILLEGAL Activating ILLEGAL ILLEGAL A10/AP ILLEGAL ILLEGAL Idle after tRFC Idle after tRFC Refreshing...
  • Page 106 ESMT M12L64164A FUNCTION TRUTH TABLE (TABLE2) Current ADDR ACTION Note CS RAS CAS WE State ( n-1 ) INVALID Exit Self Refresh Idle after tRFC (ABI) Self Exit Self Refresh Idle after tRFC (ABI) Refresh ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Self Refresh Banks...
  • Page 107 ESMT M12L64164A Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 3,Burst Length = 1 Publication Date: May 2008 Elite Semiconductor Memory Technology Inc. Revision: 3.3 29/46...
  • Page 108 ESMT M12L64164A Note : 1. All input expect CKE & DQM can be don’t care when CS is high at the CLK high going edge. 2. Bank active @ read/write are controlled by BA0, BA1. Active & Read/Write Bank A Bank B Bank C Bank D...
  • Page 109 ESMT M12L64164A Power Up Sequence C L O C K C K E H i g h l e v e l i s n e c e s s a r y R F C R F C R A S C A S A D D R K e y...
  • Page 110 ESMT M12L64164A Read & Write Cycle at Same Bank @ Burst Length = 4 C L O C K H I G H C K E R C D R A S * N o t e 2 C A S A D D R C a 0 C b 0...
  • Page 111 ESMT M12L64164A Page Read & Write Cycle at Same Bank @ Burst Length = 4 C L O C K H I G H C K E R C D R A S * N o t e 2 C A S A D D R A 1 0 / A P R D L...
  • Page 112 ESMT M12L64164A Page Read Cycle at Different Bank @ Burst Length = 4 C L O C K C K E H I G H * N o t e 1 R A S * N o t e 2 C A S R C c C B b A D D R...
  • Page 113 ESMT M12L64164A Page Write Cycle at Different Bank @ Burst Length = 4 C L O C K H I G H C K E R A S * N o t e 2 C A S A D D R R A a C A a C B b...
  • Page 114 ESMT M12L64164A Read & Write Cycle at Different Bank @ Burst Length = 4 C L O C K H I G H C K E R A S C A S A D D R R D b C D b R B c C B c R A a...
  • Page 115 ESMT M12L64164A Read & Write cycle with Auto Precharge @ Burst Length = 4 C L O C K H I G H C K E R A S C A S A D D R A 1 0 / A P C L = 2 Q A a 1 Q A a 2 Q A a 3 D D b 0...
  • Page 116 ESMT M12L64164A Clock Suspension & DQM Operation Cycle @ CAS Letency = 2 , Burst Length = 4 C L O C K C K E R A S C A S A D D R A 1 0 / A P Q a 0 Q a 1 Q a 2...
  • Page 117 ESMT M12L64164A Read interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length = Full page C L O C K H I G H C K E R A S C A S A D D R R A a C A a C A b...
  • Page 118 ESMT M12L64164A Write interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full page C L O C K H I G H C K E R A S C A S A D D R R A a C A a C A b...
  • Page 119 ESMT M12L64164A Active/Precharge Power Down Mode @ CAS Latency = 2, Burst Length = 4 C L O C K * N o t e 2 * N o t e 1 C K E * N o t e 3 R A S C A S A D D R...
  • Page 120 ESMT M12L64164A Self Refresh Entry & Exit Cycle C L O C K * N o t e 4 * N o t e 2 m i n R F C * N o t e 1 * N o t e 6 C K E * N o t e 3 * N o t e 5...
  • Page 121 ESMT M12L64164A Mode Register Set Cycle Auto Refresh Cycle C L O C K H I G H H I G H C K E * N o t e 2 R F C R A S * N o t e 1 C A S * N o t e 3 A D D R...
  • Page 122 ESMT M12L64164A PACKING DIMENSIONS 54-LEAD TSOP(II) SDRAM (400mil) (1:3) DETAIL A 0.21 REF 0.665 REF PIN1 IDENTIFIER DETAIL "A" 0.10 SEATING PLANE SECTION B-B Symbol Dimension in mm Dimension in inch Min Norm Max Min Norm Max 1.20 0.047 0.05 0.10 0.15 0.002 0.004 0.006 0.95...
  • Page 123 ESMT M12L64164A PACKING DIMENSIONS 54-BALL SDRAM ( 8x8 mm ) Symbol Dimension in mm Dimension in inch Norm Norm 1.00 0.039 0.20 0.25 0.30 0.008 0.010 0.012 0.61 0.66 0.71 0.024 0.026 0.028 Φ 0.30 0.35 0.40 0.012 0.014 0.016 7.90 8.00 8.10...
  • Page 124 ESMT M12L64164A Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication.

  • Page 125: Reference Information

    2. Reference Information 2-1 Component Descriptions 2-1-1 DVD SONY HM 313 Connector Pin Definition - 5 -...
  • Page 126 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit °C Ambient Temperature 0 ~ 70 °C Storage Temperature -55 ~ 125 Voltage on Any Pin relative to V -1.0 ~ 4.6 Voltage on V relative to V -1.0 ~ 4.6 Short Circuit Output Current Power Dissipation Soldering Temperature ⋅...

  • Page 127: Product Specifications

    3. Product S pecifications Power supply AC ~230V/50Hz Power consumption 105W Temperature -10~+40 Working Relative humidity 5%~90% environment TV System PAL/NTSC Frequency Reponse 1.5dB(20Hz~20KHz) Disc output S/N(A weight) 80dB( 1KHz Dynamic Range 70dB( 1KHz THD+NOISE 60dB(1KHz) AM frequency Range Tuner FM band Range 64MHz ~108MHz...

  • Page 128: Upgrading System And Changing The Region Code

    4. Upgrading System and Changing the Region Code MTK upgrade: 1. Name upgrade file as "MTK.BIN"(must be in big caps) 2. Record it in a CD-R/W (It can be enclosed a sub-directory which size is about 30M, and the file content can be letter or non used file.) disc Format: (advise to use the tool NERO burning ROM) Disc volume: MEDIATEK, ISO9660 LEVEL1, MODE1，not JOILET.

  • Page 129: Operating Instruction

    5. Operating Instruction Please refer to the User’s Manual for the operating instruction of the system. Maintenance & Troubleshooting How to handle discs Disc Compatibility Some discs have special To handle, clean and protect discs ● requirements for playing, with which this player Do not touch the playing side of a disc ●...

  • Page 130: Problems And Solutions

    6.Problems and Solutions If a fault occurs, first check the points listed below before taking the set for repair. If you are unable to remedy a problem by dealer or service centre. following these hints, consult your WARNING: Under no circumstances s guarantee.
  • Page 132 History Date COMMON1389J_HD850_AM5888_STBY Original release 2009.7.13 MT1389J DVD Board w/ Sanyo HD6x Series PUHs V1.1 Modify VR-CD and MDI circuit. 2009.7.30 INDEX & POWER / RESET MT1389J LQFP128 SDRAM & FLASH & MOTOR MT1389J General GPIO List AUDIO & MIC I/F Name Features Video I/F...
  • Page 133 SERVO RF DeCAP. OFF-PAGE CONNECTION 89J_3V3 DQ[0..15] RFV12-1 89J_3V3 Crystal DQ[0..15] RFVDD3 MA[0..11] MA[0..11] DV33 0.1uF 0.1uF 4.7uF/6.3v 4.7uF/6.3v 0.1uF 0.1uF FB/200 FB/200 ADACVDD 100k 100k 10uF/6.3v 10uF/6.3v DQM[0..1] 0.1uF 0.1uF DQM[0..1] BAT54C BAT54C DACVDD3 BA[0..1] 27MHz 27MHz BA[0..1] 0.1uF 0.1uF SP-A close to 89J IC...
  • Page 134 OFF-PAGE CONNECTION DV33 SR_3V3 DQ[0..15] DQ[0..15] MA[0..11] MA[0..11] CE15 CE15 CB18 CB18 100uF/6.3v 100uF/6.3v 0.1uF 0.1uF DQM[0..1] DQM[0..1] SR_3V3 BA[0..1] BA[0..1] SDCKE DCLK DCLK MA10 DQ10 DCS# MA10 DQ10 RAS# RAS# DQ10 A10/AP DQ10 DBA0 DQ11 MA11 DQ11 CAS# CAS# BA/A11 DQ11 DQ11...
  • Page 135 OFF-PAGE CONNECTION 100pF 100pF 100pF 100pF CE18 CE18 5.1k 5.1k CE19 CE19 CE20 CE20 5.1k 5.1k ASPDIF CE21 CE21 ASPDIF CENT OP_Vref LSCH 10uF/16v 10uF/16v NJM4558 OPA NJM4558 OPA OP_Vref AKIN1 AKIN1 1000pF 1000pF 10uF/16v 10uF/16v 10uF/16v 10uF/16v NJM4558 OPA NJM4558 OPA 100k 100k...
  • Page 136 VB_5V CVBS_OUT CVBS_OUT AVCC VB_5V R108 R108 3.3k 3.3k CB33 CB33 CE35 CE35 SCART1 CE36 CE36 SCART1 0.1uF 0.1uF 10uF/10v 10uF/10v [1.8uH] Close to RCA connector SCART2 SCART2 2N3904 2N3904 HSYNC HSYNC 22uF/10v 22uF/10v R111 R111 SCART_CVBSO VSYNC VSYNC 75 1% 75 1% 100pF 100pF...
  • Page 137 OFF-PAGE CONNECTION GPIO6 MCR I/F GPIO6 GPIO7 GPIO7 GPIO8 GPIO8 CON1 CON1 GPIO9 GPIO9 SDC_D0 GPIO6 R124 R124 SD-DAT2 MCR I/F MS-GND SD-DAT3 MSC_BS SDC_CMD MSC_D0 SDC_CMD R125 R125 GPIO9 MS-BS SD-CMD GPIO29 GPIO29 MS-D1(MS-VCC) SD-GND MSC_D0 MCR_3V3 MSC_BS SDC_CLK R126 R126 GPIO8...
  • Page 138 <1A AVCC Switch <50mA +P12V Switch P_5V <500mA Power Board P_12V STB_5V MPEG Board 3.3V 1.2V Motor Driver MediaTek Confidential MediaTek Confidential MediaTek Confidential MediaTek (ShenZhen) Inc. MediaTek (ShenZhen) Inc. MediaTek (ShenZhen) Inc. Title Title Title COMMON1389J_HD850_AM5888_STBY COMMON1389J_HD850_AM5888_STBY COMMON1389J_HD850_AM5888_STBY Document Number Document Number Document Number Drawn:...
  • Page 142 REVISION RECORD ECO NO: APPROVED: DATE: U903 REM3 REM-A LED-16A 100R CAPACITOR_POLB C:ORCADWINEXPRESSLIBRARYDEVICE.OLB R0603P 100P CE20 CAPACITOR_POLB C:ORCADWINEXPRESSLIBRARYDEVICE.OLB 47uF/16V 220R 220R 220R CAPACITOR_POLB C:ORCADWINEXPRESSLIBRARYDEVICE.OLB R0603P R0603P R0603P R0603P CON8X1X2.0-VS D:DVD600DVD300-862DVD300-862.DSN GPI09 GPI08 VSDA DI/O VSLK GPI013 SW_KEY E:CUSTOMERVESTELPORTABLE1000ÔÝʱVESTEL_PORTABLE1000_89E_QSI086T_V2.DSN SW_KEY E:CUSTOMERVESTELPORTABLE1000ÔÝʱVESTEL_PORTABLE1000_89E_QSI086T_V2.DSN SW_KEY E:CUSTOMERVESTELPORTABLE1000ÔÝʱVESTEL_PORTABLE1000_89E_QSI086T_V2.DSN SW10...
  • Page 144 HER303 D_11 N12490875 N12503244 AMPGND C510 TC11 R0603E C0603E TC_7 TC_7 C505 1KV102 2200U/35V L505 TC12 C514 R513 R503 1KV222 N12503179 D515 1000U/35V 560R1W +20V R0603E CAP_0B 56K2W HER303 D_11 68U400V N12491411 D511 L504 N12504209 GND_EARTH GND_EARTH HER303 22uH D_10 N12507729 C511 TC10...

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