Onkyo HTR-550 Service Manual page 48

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-1
Q201 : D707E001RFP250 (
BLOCK DIAGRAM
Data
R/W
C67x+ CPU
Data
R/W
Program
Fetch
I/O INT
Program
Cache
32K Bytes
32
I/O Interrupts MAX0
Out
SYSTEM DIAGRAM
C67x+
DSP Core
Program
Cache
Crossbar Switch
EMIF
ASYNC
FLASH
100 MHz
SDRAM
32 bit Floating-Point Digital Signal Processor
192
D1
64
256
D2
Memory
64
Controller
256
256
CSP 32
256
PMP DMP
32 32
High-Performance
Crossbar Switch
32 32
CONTROL MAX1 Events
In
dMAX
DSP
McASP0
192K
Bytes
SPI1
RAM
I2C0
McASP1
768K
Bytes McASP2
ROM
SPIO
I2C1
RTI
dMAX
PLL
Host
Microprocessor
Program/Data
JTAG EMU
RAM
192K Bytes
32
Program/Data
ROM Page1
256K Bytes
Program/Data 32
ROM Page2
256K Bytes
Program/Data
32
ROM Page3
256K Bytes
32
32
32
EMIF
Audio Zone 1
SPI or I2C
Control (optional)
Audio Zone 2
Audio Zone 3
OSC
DSP Control
SPI or I2C
TX-SR505/505E
)-1/5
McASP0
16 Serializers
32
McASP1
6 Serializers
32
McASP2
2 Serializers
32
DIT Only
32 SPI1
32 SPI0
32 I2C0
32 I2C1
32 RTI
32 PLL
CODEC, DIR,
ADC, DAC, DSD,
Network
CODEC, DIR,
ADC, DAC, DSD,
Network
Digital Out
5 Independent Audio
Zones (3 TX + 2 RX)
16 Serial Data Pins