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EN 38
8.
RAM1.0L LA
8.3
Diagram B10, TPA3101D (IC U23)
Block diagram
VBYP
AVCC
RINN
RINP
GAIN0
GAIN1
FAULT
ROSC
SYNC
MSTR/SLV
VREG
SHUTDOWN
MUTE
LINN
LINP
AGND
Pinning information
2010-Jul-02
IC Data Sheets
VBYP
AVCC
Gain
Gain
Control
VBYP
T
Adj.
Gain
Control
8
Gain
Ramp
Generator
VREG
TLL Input
Buffer
TLL Input
Buffer
Gain
VBYP
Gain
Control
Gain
48
NC
1
RINN
2
3
RINP
AGND
4
LINP
5
LINN
6
NC
7
GAIN0
8
9
GAIN1
MSTR/SLV
10
SYNC
11
NC
12
13
14
Figure 8-4 Internal block diagram and pin configuration
PWM
Logic
AVCC
VBYP
Startup
Biases
Protection
and
Logic
References
PWM
Logic
47
46
45
44
43
42
41
40
39
38
37
Exposed
15
16
17
18
19
20
21
22
23
24
PVCCR
Gate
Drive
VClamp
Gen
PVCCR
Gate
Drive
SC
Detect
Thermal
VREG
VREGok
AVCC
VCCok
PVCCL
Gate
Drive
VClamp
Gen
PVCCL
Gate
Drive
NC
36
PVCCR
35
PVCCR
34
PGNDR
33
PGNDR
32
VCLAMPR
31
VCLAMPL
30
PGNDL
29
PGNDL
28
PVCCL
27
PVCCL
26
NC
25
PVCCR
PVCCR
VCLAMPR
BSRN
ROUTN
BSRP
ROUTP
PGNDR
PVCCL
PVCCL
VCLAMPL
BSLN
LOUTN
BSLP
LOUTP
PGNDL
18930_301_100309.eps
100309
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