Page 1 TMS320C2x User's Guide 1604907-9761 revision C January 1993...
Page 2 Note: Throughout this document, TMS320C2x refers to the TMS320C25, TMS320C25-33, TMS320C25-50, TMS320E25, TMS320C26, TMS320C28 unless stated otherwise. Where applicable, ROM includes the on-chip EPROM of the TMS320E25.
Page 3 General Description General Description The TMS320 family currently consists of five generations: TMS320C1x, TMS320C2x, TMS320C3x, TMS320C4x, and TMS320C5x (see Figure 1–1). The family expansion includes enhancements of existing generations and more powerful new generations of digital signal processors. Many features are common among these generations.
Page 4 TMS320C51 Ç Ç Ç Ç Ç Ç TMS320C53 Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç TMS320C2x Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç TMS320C25 Ç Ç Ç Ç Ç Ç...
Page 5 *PGA = 68-pin grid array; PLCC = plastic-leaded chip carrier; CER = surface mount ceramic-leaded chip carrier (CER-QUAD); QFP = plastic quad flat package The TMS320C25, like all members of the TMS320C2x generation, is pro- cessed in CMOS technology. The TMS320C25 is capable of executing 10 mil- lion instructions per second.
Page 6 General Description The TMS320E25 is identical to the TMS320C25, except that the on-chip 4K-word program ROM is replaced with a 4K-word on-chip program EPROM. On-chip EPROM allows realtime code development and modification for im- mediate evaluation of system performance. The TMS320C26 is pin-for-pin and object-code compatible (except for RAM configuration instructions) with the TMS320C25.
Page 7 Key Features Key Features Key features of the TMS320C2x devices are listed below. Those that pertain to a particular device are followed by the device name within parentheses. Instruction cycle timing: 80-ns (TMS320C25-50) 100-ns (TMS320C25, TMS320E25, TMS320C26, and TMS320C28) 120-ns (TMS320C25-33)
Page 8 Key Features Global data memory interface TMS320C1x source-code upward compatibility Concurrent DMA using an extended hold operation Instructions for adaptive filtering, FFT, and extended-precision arithmetic Bit-reversed indexed-addressing mode for radix-2 FFT On-chip clock generator Single 5-V supply Power-down mode (TMS320C28 only) Device packaging: 68-pin PGA (TMS320C25) 68-lead PLCC (TMS320C25, TMS320C26, and TMS320C28)
Page 9: Typical Applications
Solid-State Answering Fetal Monitors Machines Many of the TMS320C2x features, such as single-cycle multiply/accumulate instructions, 32-bit arithmetic unit, large auxiliary register file with a separate arithmetic unit, and large on-chip RAM and ROM make the device particularly applicable in digital signal processing systems. At the same time, general-pur-...
Page 10 Typical Applications The TMS320C2x has the flexibility to be configured to satisfy a wide range of system requirements. This allows the device to be applied in systems currently using costly bit-slice processors or custom ICs. These are examples of such...
Page 11 Introduction 1-10...
Page 12 Chapter 2 Pinouts and Signal Descriptions The TMS320C2x generation digital signal processors are available in one or more of four package types. The TMS320C25 (40-MHz version only) is avail- able in a 68-pin grid array (PGA) package. The TMS320C25 (33-MHz, 40-MHz, and 50-MHz versions) and the TMS320C26 are available in a plastic 68-lead chip carrier (PLCC) package.
Page 13 TMS320C2x Pinouts Figure 2–1 shows pinouts of the PGA, PLCC, and CER-QUAD packages for the TMS320C2x devices. Note that the pinout and external dimensions of PLCC and CER-QUAD are identical. Figure 2–2 shows preliminary pinouts of the QFP package for the TMS320C28 device.
Page 14 TMS320C2x Pinouts Figure 2–2. TMS320C28 Pin Assignments 80-Pin PH Quad Flat Package † (Top View) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 IACK WAKEUP V SS V CC V CC CLKX...
Page 15 TMS320C2x Signal Descriptions TMS320C2x Signal Descriptions The signal descriptions for the TMS320C2x devices are provided in this sec- tion. Table 2–1 lists each signal, its pin location (PGA, PLCC, and CER- QUAD), function, and operating mode(s): that is, input, output, or high-imped- ance state as indicated by I, O, or Z.
Page 16 HOLD A7/67 Hold input. When this signal is asserted, the TMS320C2x places the data, address, and control lines in the high-impedance state. HOLDA E10/55 Hold acknowledge signal.
Page 17 C10/59 Microstate complete signal. Asserted low and valid only during CLKOUT1 low when the TMS320C2x has just completed a memory operation, such as an instruction fetch or a data memory read/write. MSC can be used to generate a one wait-state READY signal for slow memory.
Page 18 TMS320C2x Signal Descriptions Table 2–1. TMS320C2x Signal Descriptions (Continued) I/O/Z ‡ Signal Description (PGA/PLCC † ) Serial Port Signals CLKR B9/64 Receive clock input. External clock signal for clocking data from the DR (data receive) pin into the RSR (serial port receive shift register).
Page 19 Pinouts and Signal Descriptions...
Page 20: Read This First
How to Use This Manual This document contains the following chapters: Chapter 1 Introduction Description and key features of the TMS320C2x generation of digital signal processors. Chapter 2 Pinouts and Signal Descriptions Package drawings for TMS320C2x devices. Functional listings of the signals, their pin locations, and descriptions.
Page 21 Discussion of ROM codes (mask options) and the procedure for implementation. Appendix J Quality and Reliability Discussion of Texas Instruments quality and reliability criteria for evaluating performance. Appendix K Development Support Listings of the hardware and software available to support the TMS320C2x devices. Read This First...
Page 22 Style and Symbol Conventions Style and Symbol Conventions This document uses the following conventions. Program listings, program examples, interactive displays, filenames, and symbol names are shown in a special typeface similar to a typewriter’s. Examples use a bold version of the special typeface for emphasis;...
Page 23 Style and Symbol Conventions / Information About Cautions Braces ( { and } ) indicate a list. The symbol | (read as or ) separates items within the list. Here’s an example of a list: Unless the list is enclosed in square brackets, you must choose one item from the list.
Page 24 Related Documentation From Texas Instruments Related Documentation From Texas Instruments General Digital Signal Processing: Antoniou, Andreas, Digital Filters: Analysis and Design . New York, NY: McGraw-Hill Company, Inc., 1979. Brigham, E. Oran, The Fast Fourier Transform. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1974.
Page 25 VAX, VMS, and Ultrix are trademarks of Digital Equipment Corp. PC-DOS is a trademark of International Business Machines Corp. Sun 3 is a trademark of Sun Microsystems, Inc. UNIX is a registered trademark of UNIX Systems Laboratories. XDS is a trademark of Texas Instruments Incorporated. Read This First viii...
Page 26 If You Need Assistance. . . If you want to. . . Do this. . . Request more information about Write to: Texas Instruments Digital Signal Texas Instruments Incorporated Processing (DSP) products Market Communications Manager, MS 736 P.O. Box 1443 Houston, Texas 77251–1443...
Page 27 Read This First...
Page 28 ............TMS320C2x Signal Descriptions .
Page 29 Contents Interrupts ..............3-59 3.8.1 Interrupt Operation...
Page 30 Contents Advanced Arithmetic Operations ..........5-46 5.6.1 Overflow Management...
Page 31 ............TMS320C2x Instruction Cycle Timings .
Page 32: Table Of Contents
3-26 3–13 Central Arithmetic Logic Unit (CALU), TMS320C2x ....... 3-29 3–14...
Page 33 Figures 3–37 Burst-Mode Serial Port Transmit Operation ........3-68 3–38 Burst-Mode Serial Port Receive Operation...
Page 34 6-41 6–23 Synchronous Timing of TLC32040 to TMS320C2x ....... .
Page 35 E–1 TMS320C2x Instructions by Cycle Class .........
Page 36 J–2 TMS320C2x Transistors ............
Page 37 Examples Examples 5–1 Processor Initialization (TMS320C25) ..........5–2 Processor Initialization (TMS320C26) .
Page 38 Examples 5–37 Using LACT for Denormalization ..........5-61 5–38 Row Times Column...
Page 39 Table of Contents xxii...
Page 40 Chapter 3 Architecture The architectural design of the TMS320C2x emphasizes overall system speed, communication, and flexibility in processor configuration. Control sig- nals and instructions provide block memory transfers, communication to slow- er off-chip devices, and multiprocessing implementations. Single-cycle multi- ply/accumulate instructions, two large on-chip RAM Blocks, eight auxiliary...
Page 41 Instructions can be executed from the EPROM at full speed. The EPROM is equipped with a security mechanism allowing you to protect proprietary in- formation. A programming adapter socket is available from Texas Instruments that provides 68- to 28-pin conversion for programming with standard PROM programmers.
Page 42: Tms320C2X Simplified Block Diagram
Shifters Address (16) Timer Arithmetic Logic Unit. The TMS320C2x performs 2s-complement arithmetic using the 32-bit ALU and accumulator. The ALU is a general-purpose arithme- tic unit that operates using 16-bit words taken from data RAM or derived from immediate instructions or using the 32-bit result of the multiplier’s product reg- ister.
Page 43 STRB signal provides a timing signal to control the transfer. When us- ing on-chip program RAM, ROM/EPROM, or high-speed external program memory, the TMS320C2x runs at full speed without wait states. The use of a READY signal allows wait-state generation for communicating with slower off- chip memories.
Page 44 (DMA) to its external program/data memory using the HOLD and HOLDA sig- nals. Another processor can take complete control of the TMS320C2x external memory by asserting HOLD low. This causes the TMS320C2x to place its ad- dress, data, and control lines in the high-impedance state. Signaling between the external processor and the TMS320C2x can be performed by using inter- rupts.
Page 45: Functional Block Diagram
Refer to Section 3.3, Internal Hardware Summary , for definitions of the symbols used in Figure 3–2. The block diagram also shows all of the TMS320C2x interface pins. Figure 3–3 shows the block diagram of the TMS320C26.
Page 46: Tms320C25/E25 Block Diagram
Functional Block Diagram Figure 3–2. TMS320C25/E25 Block Diagram SYNC Program Bus PFC(16) QIR(16) IR(16) STRB READY STO(16) ST1(16) RPTC(8) HOLD HOLDA IFR(6) MCS(16) PC(16) CLKR IACK CLKX Address Stack MP/MC (8 x 16) RSR(16) Program INT(2-0) ROM/ XSR(16) EPROM DRR(16) A15-A0 (4096 DXR(16)
Page 47: Tms320C26 Block Diagram
Functional Block Diagram Figure 3–3. TMS320C26 Block Diagram SYNC Program Bus QIR(16) PFC(16) IR(16) STRB READY STO(16) ST1(16) RPTC(8) HOLD HOLDA IFR(6) MCS(16) PC(16) CLKR IACK CLKX Stack Address MP/MC RSR(16) Bootload INT(2-0) Program XSR(16) DRR(16) A15-A0 (256 DXR(16) Instruction TIM(16) PRD(16) IMR(6)
Page 48: Tms320C2X Internal Hardware
This hardware-intensive approach provides computing power previously unavailable on a single chip. Table 3–1 presents a summary of the TMS320C2x internal hardware. This summary table, which includes the internal processing elements, registers, and buses, is alphabetized within each functional grouping. All of the symbols used in this table correspond to the symbols used in the block diagram of Section 3.2, the succeeding block diagrams in this section, and the text...
Page 49 Internal Hardware Summary Table 3–1. TMS320C2x Internal Hardware (Continued) Unit Symbol Function Instruction Register IR(15–0) A 16-bit register used to store the currently executing instruction. Interrupt Flag Register IFR(5–0) A 6-bit flag register used to latch the active-low external user interrupts INT(2–0), the internal interrupts XINT/RINT (serial port transmit/re-...
Page 50 Internal Hardware Summary Table 3–1. TMS320C2x Internal Hardware (Concluded) Unit Symbol Function Serial Port Receive Shift RSR(15–0) A 16-bit register used to shift in serial port data from the RX pin. RSR Register contents are sent to the DRR after a serial transfer is completed. RSR is not directly accessible through software.
Page 51 Memory Organization Memory Organization The TMS320C2x provides a total of 544 16-bit words of on-chip data RAM, of which 288 words are always data memory and the remaining 256 words may be configured as either program or data memory. The TMS320C26 provides a total of 1568 words of 16 bit on-chip RAM, divided into four separate bolcks (B0, B1, B2, and B3).
Page 52: Tms320C2X On-Chip Data Memory
EPROM. Either on-chip ROM or EPROM allows program execution at full speed without the need for high-speed external program memory. The use of this memory also allows the external data bus to be freed for access of external data memory. Figure 3–4. TMS320C2x On-Chip Data Memory From From Program Counter...
Page 53: Tms320C26 On-Chip Data Memory
Mapping of the first 4K-word block of off-chip/on-chip program memory is user- selectable by means of the MP/MC (microprocessor/microcomputer) pin on the TMS320C2x. Setting MP/MC to a high maps in the block of off-chip memory; holding the pin at a low maps in the block of on-chip ROM. Conse- quently, compatible products that depend upon external memory from the ROM can be manufactured in a shorter time frame than the TMS320C2x.
Page 54 This delay is one fetch cycle if execution is from internal program RAM. On the TMS320C2x, there is a delay of two fetch cycles if execution is from ROM or external program memory.
Page 55 Memory Organization The on-chip program ROM can be mapped into the lower 4K words of program memory. This ROM is enabled when MP/MC is set to a logic low. To disable the on-chip ROM and use these lower addresses externally, MP/MC must be set to a logic high.
Page 56: Tms320C25/26 Memory Blocks
Memory Organization Table 3–2. TMS320C25/26 Memory Blocks Configured As Data Memory TMS320C26 TMS320C25 Address Address Address Address Block Pages Decimal Hexadecimal Pages Decimal Hexadecimal 96–127 0060h–00F7h 96–127 0060h–007Fh 4–7 512–1023 0200h–03FFh 4–5 512–768 0200h–02FFh 8–11 1024–1536 0400h–05FFh 6–7 769–1024 0300h–03FFh 12–15 1537–2048 0600h–07FFh...
Page 57: Comparison Of Internal Ram Configured As Data Space
Memory Organization Figure 3–6. Comparison of Internal RAM Configured as Data Space TMS320C25 TMS320C28 TMS320C26 Memory-Mapped Memory-Mapped Registers Registers Reserved Reserved 05Fh 05Fh 060h 060h 07Fh 07Fh 080h 080h Reserved Reserved 01FFh 01FFh 0200h 0200h 2FFh 300h 03FFh 03FFh 0400h 0400h 05FFh 0600h...
Page 58: Tms320C2X Memory Maps
Memory Organization Figure 3–8. TMS320C2x Memory Maps (a) Memory Maps After a CNFD Instruction Program Program Data 0 (0000h ) 0 (0000h ) 0 (0000h ) Interrupts On-Chip Interrupts and Reserved Memory-Mapped and Reserved (On-Chip Registers (External) 31 (001Fh )
Page 59: Tms320C26 Memory Maps
Memory Organization Figure 3–9. TMS320C26 Memory Maps Program Program Data (0000h ) (0000h ) (0000h ) On-Chip Interrupts Interrupts Memory-Mapped and Reserved and Reserved Registers Bootload ROM (External) (001Fh) (00FFh) (0005h ) (0020h ) (0100h ) (0006h ) Page 0 Reserved Reserved (005Fh)
Page 60 Memory Organization Figure 3–9. TMS320C26 Memory Maps (continued) Program Program Data (0000h ) (0000h ) (0000h ) Interrupts Interrupts On-Chip and Reserved Memory-Mapped and Reserved Bootload ROM Registers (External) (001Fh) (00FFh) (0005h ) (0100h ) (0020h ) (0006h ) Page 0 Reserved Reserved (005Fh)
Page 61: Memory-Mapped Registers
Global memory allocation register 3.4.6 Auxiliary Registers The TMS320C2x provides a register file containing eight auxiliary registers (AR0–AR7). This section discusses each register’s function and how an auxil- iary register is selected and stored. The auxiliary registers may be used for indirect addressing of data memory or for temporary data storage.
Page 62: Indirect Auxiliary Register Addressing Example
0 0 0 8 h 8 4 3 D h The auxiliary register files (AR0–AR7 on the TMS320C2x) are connected to the auxiliary register arithmetic unit (ARAU), shown in Figure 3–11. The ARAU may autoindex the current auxiliary register while the data memory location is being addressed.
Page 63: Auxiliary Register File
Memory Organization Figure 3–11. Auxiliary Register File Auxiliary Register 7 (AR7) (16) Auxiliary Register 6 (AR6) (16) Auxiliary Register 5 (AR5) (16) Auxiliary Register 4 (AR4) (16) Auxiliary Auxiliary Auxiliary Register 3 (AR3) (16) Register Register Auxiliary Register 2 (AR2) (16) Pointer Buffer 8 LSB...
Page 64: Memory Organization
3.4.7 Memory Addressing Modes The TMS320C2x can address a total of 64K words of program memory and 64K words of data memory. The on-chip data memory is mapped into the 64K- word data memory space. The on-chip ROM in the TMS320C25 is mapped into the program memory space when in the microcomputer mode.
Page 65: Methods Of Instruction Operand Addressing
Memory Organization Figure 3–12. Methods of Instruction Operand Addressing Instruction Direct Addressing Opcode Operand Instruction Indirect Addressing Opcode AR (ARP) Operand Instruction Immediate Operand Opcode Operand Instruction Operand PC+1 In the direct addressing mode, the 9-bit data memory page pointer (DP) points to one of 512 pages, each page consisting of 128 words.
Page 66 Implemented in on-chip RAM, the DMOV (data move) function on the TMS320C2x is equivalent to that of the TMS320C1x. DMOV allows a word to be copied from the currently addressed data memory location in on-chip RAM to the next higher location while the data from the addressed location is being operated upon in the same cycle (for example, by the CALU).
Page 67: Central Arithmetic Logic Unit (Calu)
Central Arithmetic Logic Unit (CALU) Central Arithmetic Logic Unit (CALU) The TMS320C2x central arithmetic logic unit (CALU) contains a 16-bit scaling shifter, a 16 16-bit parallel multiplier, a 32-bit arithmetic logic unit (ALU), a 32-bit accumulator (ACC), and additional shifters at the outputs of both the ac- cumulator and the multiplier.
Page 68: Central Arithmetic Logic Unit (Calu), Tms320C2X
Central Arithmetic Logic Unit (CALU) Figure 3–13. Central Arithmetic Logic Unit (CALU), TMS320C2x Program Bus Data Bus TR(16) Shifter Multiplier SX or 0 (0-16) PR(32) Shifter(–6, 0, 1, 4) or 0 ALU(32) ACCH(16) ACCL(16) SFL(0-7) Data Bus 3-29...
Page 69 Shifters at the output of the accumulator provide a left-shift of 0 to 7 places on the TMS320C2x. This shift is performed while the data is being transferred to the data bus for storage. The contents of the accumulator re- main unchanged.
Page 70: Examples Of Tms320C25 Carry Bit Operation
(Note that logical operations cannot result in overflow.) The TMS320C2x can execute a variety of branch instructions that depend on the status of the ALU and accumulator. These instructions include the BV (branch on overflow) and BZ (branch on accumulator equal to zero).
Page 71 The carry bit is set to one on a hardware reset. The SFL and SFR (in-place one-bit shift to the left/right) instructions on the TMS320C2x and the ROL and ROR (rotate to the left/right) instructions on the TMS320C25 implement shifting or rotating of the contents of the accumulator through the carry bit.
Page 72: Pm Shift Modes
32 bits. After the multiplication of two 16-bit numbers, the 32-bit product is loaded into the PR on the TMS320C2x. The product from the PR may be transferred to the ALU.
Page 73 Central Arithmetic Logic Unit (CALU) Left shifts specified by the PM value are useful for implementing fractional arithmetic or justifying fractional products. For example, the product of either two normalized, 16-bit, 2s-complement numbers or two Q15 numbers con- tains two sign bits, one of which is redundant. Q15 format, one of the various types of Q format, is a number representation commonly used when perform- ing operations on noninteger numbers (see subsection 5.6.7 for an explana- tion and examples of Q15 representation).
Page 74: Program Counter, Stack, And Related Hardware
System Control System Control System control on the TMS320C2x is supported by the program counter, hard- ware stack, PC-related hardware, the external reset signal, interrupts (see Section 3.8), the status registers, the on-chip timer, and the repeat counter. The following sections describe the function of each of these components in system control and pipeline operation.
Page 75 PC is incremented once more beyond the location of the branch address. The TMS320C2x also has a feature that allows the execution of the next single instruction N+1 times. N is defined by loading an 8-bit counter RPTC (repeat counter).
Page 76 Thus, during any given cycle, three different instructions can be active, each at a different stage of completion, resulting in the three-level pipeline on the TMS320C2x. The difference in pipeline levels does not necessarily affect instruction execu- tion speed, but merely changes the fetch/decode sequence.
Page 77: Three-Level Pipeline Operation (Tms320C25)
System Control Figure 3–16. Three-Level Pipeline Operation (TMS320C25) CLKOUT1 prefetch decode execute Pipelining is reduced to two levels when execution is from internal program RAM due to the fact that an instruction in internal RAM can be fetched and de- coded in the same cycle.
Page 78: Tms320C25 Standard Pipeline Operation
System Control The TMS320C25 executes most of its instructions in a single cycle because all the instructions are straight decodes and highly pipelined as opposed to mi- crocode. The basic pipeline operation is 3.25 cycles deep where the device sequence on any given cycle is fetching the third instruction, decoding the se- cond instruction, and executing the first.
Page 79: Instruction Pipeline Sequence
System Control Table 3–5. Instruction Pipeline Sequence Cycle Q Phase Operation New PC is output on address bus External read of instruction External read of instruction External read of instruction Instruction decode Instruction decode/ARAU execution On-chip RAM access/ARAU execution On-chip RAM access/load new AR value/update ARP ALU execution ALU execution Load accumulator...
Page 80: Pipeline Operation Of Add Followed By Sacl
System Control Figure 3–19. Pipeline Operation of ADD Followed by SACL Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Clock CLKOUT1 CLKOUT2 STRB Address ADD *+12, AR4 SACL *0,3, AR2 Data Decode SACL ADD/Read SACL Write Execute Dummy Load AUXREG ARx +1...
Page 81: Pipeline Operation With Wait States
System Control Figure 3–20. Pipeline Operation With Wait States Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Clock CLKOUT1 CLKOUT2 STRB Address ADD *+,12, AR4 Wait State SACL *0,3, AR2 Wait State OR *+ Data Decode SACL ADD Read SACL/Write Execute Dummy...
Page 82: Pipeline With External Data Bus Conflict
System Control Figure 3–21. Pipeline With External Data Bus Conflict Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Clock CLKOUT1 CLKOUT2 STRB Address SACL *0-,3, AR2 LAC *+ Data Space Data Space Data Write Read Decode SACL EXTRAM SACL Write LAC Read Execute...
Page 83: Pipeline Operation Of Branch To On-Chip Ram
System Control Figure 3–22. Pipeline Operation of Branch to On-Chip RAM Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Clock CLKOUT1 CLKOUT2 STRB Address 0FF00h ADD *+, 12,AR4 Data Decode ADDH SUB*-,12,AR4 INTRAM ADDH *+ DATARAM SUB Read Status Execute AUXREG...
Page 84: Pipeline Operation Of Ret From On-Chip Ram
System Control Figure 3–23. Pipeline Operation of RET From On-Chip RAM Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Clock CLKOUT1 CLKOUT2 STRB Address ADD *+, 12, AR4 SUB *0-, 3, AR2 OR *+ Data Decode INTRAM DATARAM Status Execute AUXREG...
Page 85 System Control Reset. The reset interrupt is a totally nonmaskable interrupt. When executed, it stops operation of the pipeline and flushes the unexecuted parts. The reset pulse must be at least three CLKOUT cycles wide. After the second CLKOUT cycle has completed (before the third rising edge of CLKOUT1), the device has brought all outputs into a high-impedance state.
Page 86 Reset Reset (RS) is a nonmaskable external interrupt that can be used at any time to put the TMS320C2x into a known state. Reset is typically applied after pow- erup when the machine is in a random state. Driving the RS signal low causes the TMS320C2x to terminate execution and forces the program counter to zero.
Page 87 5) All interrupts are disabled by setting the INTM (interrupt mode) bit to 1. (Note that RS is nonmaskable.) The interrupt flag register (IFR) is reset to all zeros. 6) Status bits are set: For all TMS320C2x devices, 0 OV, 1 XF, 0 FO, 0...
Page 88: Tms320C2X Status Register Organization
Upon release of HOLD and RS, execution starts from location zero. The TMS320C2x can be held in the reset state indefinitely. Note: Reset does not have internal Schmidt hysteresis. To insure proper reset op- eration, avoid slow rise and fall times.
Page 89: Tms320C26 Status Register Organization
System Control Figure 3–25 shows the two status registers of the TMS320C26. All bits, be- sides the redefined CNF0 (CNF in the TMS320C25) and the new CNF1 bit, are unchanged. Figure 3–25. TMS320C26 Status Register Organization OV OVM INTM CNF0 TC SXM C CNF1 HM FSM XF FO TXM Table 3–6.
Page 90 System Control Table 3–6. Status Register Field Definitions (Continued) Field Function Hold mode bit. When HM = 1, the processor halts internal execution when acknowledging an active HOLD. When HM = 0, the processor may continue execution out of internal program memory but puts its external interface in a high-impedance state.
Page 91: Timer Block Diagram
System Control 3.6.5 Timer Operation The TMS320C2x provides a memory-mapped 16-bit timer (TIM) register and a 16-bit period (PRD) register, as shown in Figure 3–26. The on-chip timer is a down counter that is continuously clocked by CLKOUT1. Figure 3–26. Timer Block Diagram...
Page 92 System Control If the timer is not used, either TINT is to be masked or all maskable interrupts are to be disabled by a DINT instruction. The PRD register can then be used as a general-purpose data memory location. If TINT is used, the PRD and TIM registers are to be programmed before unmasking the TINT.
Page 93: External Memory And I/O Interface
The R/W (read/write) signal controls the direction of the transfer, and STRB (strobe) provides a timing signal to control the transfer. The TMS320C2x I/O space consists of 16 input and 16 output ports. These ports provide the full 16-bit parallel I/O interface via the data bus on the device.
Page 94 Note, however, that the TMS320C2x has the capabil- ity of executing write to external data memory instruc- tions in a single cycle when program memory is inter- nal (two cycles are required if program memory is also external).
Page 95: Four-Phase Clock
CLKOUT2 3.7.3 General-Purpose I/O Pins (BIO and XF) The TMS320C2x has two general-purpose pins that are software-controlled. The BIO pin is a branch control input pin, and the XF pin is an external flag out- put pin. The BIO pin is useful for monitoring peripheral device status. It is especially useful as an alternative to using an interrupt when it is necessary not to disturb time-critical loops.
Page 96: Bio Timing Diagram
External Memory and I/O Interface In Figure 3–28, BIO is sampled at the end of Q4. The timing diagram shown is for a sequence of single-cycle, single-word instructions without branches lo- cated in external memory. Because of variations in pipelining due to instruc- tions prior to and following the BIOZ instruction, this timing may vary.
Page 97: External Flag Timing Diagram
External Memory and I/O Interface Figure 3–29. External Flag Timing Diagram CLKOUT1 STRB A15–A0 Valid Valid Valid Valid (SXF or RXF) fetch (SXF) (RXF) Notes: 1) N is the program memory location for the current instruction. 2) This example shows only the execution of single-cycle instructions fetched from external program memory. Architecture 3-58...
Page 98: Interrupt Locations And Priorities
RS (reset) signal. The RS signal is not stored in the IFR. No instructions are provided for reading from or writing to the IFR. The TMS320C2x has a memory-mapped interrupt mask register (IMR) for masking external and internal interrupts. The layout of the register is shown in Figure 3–30.
Page 99: Interrupt Mask Register (Imr)
IFR until the repeat counter (RPTC) decrements to zero, and then the interrupt is processed. Even if the interrupt is not used while the TMS320C2x is processing the RPT or RPTK, the interrupt will still be latched by IFR and pending until RPTC decrements to zero.
Page 100: Internal Interrupt Logic Diagram
Interrupts Figure 3–31. Internal Interrupt Logic Diagram IACK IACK DINT From Data +5 V Interrupt Mask Interrupt Register Mode Interrupt (INTM) Edge Idle EINT (0, 1, IACK or 2) Priority Decode SYNC Interrupt Interrupt Flag Processor Register Interrupt Active Machine State Logic for each external interrupt From...
Page 101: Interrupt Timing Diagram (Tms320C25)
Interrupts Figure 3–32 shows an interrupt, interrupt acknowledge, and various other sig- nals for the special case of single-cycle instructions. An interrupt generated during the current (N) fetch cycle still allows the fetch and execution of that instruction. The N+1 and N+2 instructions are also fetched, then discarded, and the address N+1 is pushed onto the top of the stack.
Page 102: Serial Port Bits, Pins, And Registers
The serial port may also be used for inter- communication between processors in multiprocessing applications. Both receive and transmit operations are double-buffered on the TMS320C2x, thus allowing a continuous bit stream even if FSX is an output. The use of the frame sync mode (FSM) bit provides continuous operation that, once initiated, requires no further frame synchronization pulses.
Page 103: The Drr And Dxr Registers
CLKX. If TXM = 0, the FSX pin becomes an input pin. The TMS320C2x then waits for an external synchronization pulse before beginning transmission. On a reset, TXM is set to zero, configuring FSX to be an input.
Page 104: Serial Port Block Diagram
Serial Port 3.9.1 Transmit and Receive Operations The transmit and receive sections of the serial port are implemented separate- ly to allow independent transmit and receive operations. Externally, the serial port interface is implemented using the six serial port pins. Figure 3–34 shows the registers and pins used in transmit and receive operations.
Page 105: Serial Port Transmit Timing Diagram
The transmit timing diagram is shown in Figure 3–35. The transmit operation begins when data is written into the data transmit register (DXR). The TMS320C2x begins transmitting data when the frame synchronization pulse (FSX) goes low while CLKX is high or going high. The data, starting with the MSB, is then shifted out via the DX pin with the rising edge of CLKX.
Page 106: Serial Port Receive Timing Diagram
(in the continuous transmission mode), only the last value written will be loaded into XSR for the next transmit operation. When the TMS320C2x is reset, TXM is cleared to zero, and DX is placed in the high-impedance state. Any transmit or receive operation that is in progress when the reset occurs is terminated.
Page 107: Burst-Mode Serial Port Transmit Operation
Serial Port 3.9.3 Burst-Mode Operation In burst-mode serial port operation, transfers are separated in time by periods of no serial port activity (the serial port does not operate continuously). For burst-mode operation, FSM must be set to one. Timing of the serial port in this mode of operation is shown in Figure 3–37 and Figure 3–38.
Page 108: Byte-Mode Drr Operation (Tms320C25)
Serial Port When TXM = 1 (FSX is an output) and the serial port register DXR is loaded, a framing pulse is generated on the next rising edge of CLKX. The XSR is loaded with the current contents of DXR while FSX is high and CLKX is low. Transmission begins when FSX goes low while CLKX is high or is going high.
Page 109: Serial Port Transmit Continuous Operation (Fsm = 1)
Serial Port Figure 3–40. Serial Port Transmit Continuous Operation (FSM = 1) CLKX (TXM=1) (F0=1) XINT Loaded Loaded Loaded Loaded With B With C Figure 3–41. Serial Port Receive Continuous Operation (FSM = 1) CLKR (F0=1) RINT Read Read Loaded Loaded From RSR From RSR...
Page 110 Serial Port 3.9.5 Continuous Operation Without Frame Sync Pulses (TMS320C25) The continuous mode of operation on the TMS320C25 allows transmission and reception of a continuous bit stream without requiring frame sync pulses every 8 or 16 bits. This mode is selected by setting FSM = 0. Figure 3–42 and Figure 3–43 show operation of the serial port for both states of TXM to illustrate differences in operation for each case.
Page 111: Serial Port Transmit Continuous Operation (Fsm = 0)
Serial Port Figure 3–42. Serial Port Transmit Continuous Operation (FSM = 0) CLKX (TXM=1) (TXM=0) (F0=1) XINT RFSM Loaded With B Loaded Loaded Loaded From DXR With C Figure 3–43. Serial Port Receive Continuous Operation (FSM = 0) CLKR (F0=1) RINT Read RFSM...
Page 112 Serial Port 3.9.6 Initialization of Continuous Operation Without Frame Sync Pulses FSM is normally initialized during an XINT or RINT service routine to enable or disable FSX and FSR, respectively, for the next serial port operation. It is necessary to start this mode with FSM = 1 so that the first data transferred out of the serial port is the data written to the DXR register.
Page 113: Continuous Transmit Operation Initialization
Serial Port Figure 3–44. Continuous Transmit Operation Initialization CLKX (TXM=1) (TXM=0) (F0=1) XINT RFSM Loaded Reloaded Loaded With A Figure 3–45. Continuous Receive Operation Initialization CLKR (F0=1) RINT RFSM Loaded From RSR Architecture 3-74...
Page 114: Multiprocessing And Direct Memory Access (Dma)
Multiprocessing and Direct Memory Access (DMA) 3.10 Multiprocessing and Direct Memory Access (DMA) The flexibility of the TMS320C2x allows configurations to satisfy a wide range of system requirements. Some of the system configurations using the TMS320C2x are as follows: A standalone system (single processor),...
Page 115: Synchronization Timing Diagram (Tms320C25)
A memory-mapped global memory allocation register (GREG) specifies part of the TMS320C2x’s data memory as global external memory. GREG, which is memory-mapped at data memory address location 5, is an eight-bit register connected to the eight LSBs of the internal D bus. The upper eight bits of loca- tion 5 are nonexistent and read as 1s.
Page 116: Global Memory Access Timing
External logic then arbitrates for control of the global memory, asserting READY when the TMS320C2x has control. The length of the memory cycle is controlled by the READY line. One wait-state timing is shown in Figure 3–47. Note that all signals not shown have the same timing as in the normal read or write case.
Page 117 (INT2 – INT0), HOLD is not a latched input. The external device must keep HOLD low until it receives a HOLDA from the TMS320C2x. If the TMS320C2x is in the middle of a multicycle instruction, it will finish the instruction before entering the hold state. After the instruction is completed, the buses are placed in the high-impedance state.
Page 118 Multiprocessing and Direct Memory Access (DMA) The operating mode is selected by the HM (hold mode) status register bit on the TMS320C25. The HOLD signal is pulled low, as shown in the first part of Figure 3–48. When HM = 1, the TMS320C25 halts program execution and en- ters the hold state directly.
Page 119: Tms320C25 Hold Timing Diagram
Multiprocessing and Direct Memory Access (DMA) Figure 3–48. TMS320C25 Hold Timing Diagram CLKOUT1 STRB HOLD A15–A0 PS, DS, Valid Valid or IS D15–D0 fetch execute HOLDA Notes: 1) N is the program memory location for the current instruction. 2) This example shows only the execution of single-cycle instructions fetched from external program memory. Architecture 3-80...
Page 120 Multiprocessing and Direct Memory Access (DMA) Figure 3–48. TMS320C25 Hold Timing Diagram (Continued) CLKOUT1 STRB HOLD A15–A0 PS, DS, Valid Valid Valid or IS D15-D0 fetch Dummy execute HOLDA Notes: 3) N is the program memory location for the current instruction. 4) This example shows only the execution of single-cycle instructions fetched from external program memory.
Page 121: 3.11 General Description Of The Tms320C26
General Description of the TMS320C26 3.11 General Description of the TMS320C26 The TMS320C26 is a spin-off of the TMS320C25. It is processed in CMOS technology, is capable of an instruction cycle time of 100 ns, and is pin-for-pin and object code-compatible with the TMS320C25, with the exception of the instructions for on-chip-memory configuration.
Page 122: 3.12 General Description Of The Tms320C28
General Description of the TMS320C28 3.12 General Description of the TMS320C28 The TMS320C28 is the newest member of the TMS320C2x family. Like the TMS320C26, it is also processed in CMOS technology, is capable of 100-ns instruction cycle time, and is object code-compatible with the TMS320C25.
Page 123 Architecture 3-84...
Page 124: Assembly Language Instructions
Running Title—Attribute Reference Chapter 4 Assembly Language Instructions The TMS320C2x instruction set supports numeric-intensive signal processing operations as well as general-purpose applications, such as multiprocessing and high-speed control. TMS320C1x source code is upward-compatible with TMS320C2x source code. The TMS320C26 is similar to the TMS320C25 except for its internal memory configuration.
Page 125 TMS320C2x device or by using a development tool. Thus, it is critical that all programs initialize the data page pointer in software.
Page 126: Direct Addressing Block Diagram
Memory Addressing Modes Figure 4–1 illustrates how the 16-bit data address is formed. Figure 4–1. Direct Addressing Block Diagram Data Bus (16) DP (9) 7 LSBs From Instruction Register (IR) Direct addressing can be used with all instructions except CALL, the branch instructions, immediate operand instructions, and instructions with no oper- ands.
Page 127: Indirect Addressing Block Diagram
LAR (load auxiliary register), LARK (load auxilia- ry register immediate), and LRLK (load auxiliary register long immediate). The auxiliary registers on the TMS320C2x can be modified by ADRK (add to auxil- iary register short immediate) or SBRK (subtract from auxiliary register short immediate).
Page 128 ARP. The adjustment may be an increment or decrement by one, or it may be based upon the contents of AR0. Bit-reversed addressing modes on the TMS320C2x allow efficient I/O to be performed for the resequencing of data points in a radix-2 FFT program. The direction of carry propagation in the ARAU is reversed when this mode is se- lected and AR0 is added to/subtracted from the current auxiliary register.
Page 129: Indirect Addressing Arithmetic Operations
Memory Addressing Modes sponding to one-half of the array size, and AR(ARP) be set to the base address of the data (the first data point). See subsection 5.7.4 for an FFT example using bit-reversed addressing modes. Indirect addressing can be used with all instructions except immediate oper- and instructions and instructions with no operands.
Page 130: Bit Fields For Indirect Addressing
Memory Addressing Modes Table 4–2 shows the bit fields, notation, and operation used for indirect ad- dressing. For some instructions, the notation in Table 4–2 includes a shift code: for example, *0+,8,3 where 8 is the shift code and Y = 3. Table 4–2.
Page 131 Immediate Addressing Mode In immediate addressing, the instruction word(s) contains the value of the im- mediate operand. The TMS320C2x has both single-word (8-bit and 13-bit constant) short immediate instructions and two-word (16-bit constant) long im- mediate instructions. The immediate operand is contained within the instruc- tion word itself in short immediate instructions.
Page 132 Memory Addressing Modes ADDK Add to accumulator short immediate (8-bit absolute constant) ADRK Add to auxiliary register short immediate (8-bit absolute constant) LACK Load accumulator short immediate (8-bit absolute constant) LARK Load auxiliary register short immediate (8-bit absolute constant) LARP Load auxiliary register pointer (3-bit constant) LDPK Load data memory page pointer immediate (9-bit...
Page 133 Memory Addressing Modes Example of long immediate addressing format: ADLK 16384,2 Add to the accumulator the value 16384 with a shift to the left of two, effectively adding 65536 to the contents of the accumulator. The ADLK instruction uses the word following the instruction opcode as the immediate operand.
Page 134 Instruction Set Instruction Set The following sections list the symbols and abbreviations used in the instruc- tion set summary and in the instruction descriptions. The complete instruction set summary is organized according to function. A detailed description of each instruction is listed in the instruction set summary. 4.2.1 Symbols and Abbreviations Table 4–3 lists symbols and abbreviations used in the instruction set summary...
Page 135: Instruction Symbols
Instruction Set Table 4–3. Instruction Symbols Symbol Meaning Port address Accumulator Auxiliary register pointer buffer Auxiliary register n (AR0, AR1 assembler symbols equal to 0 or 1) Auxiliary register pointer 4-bit field specifying a bit code Branch control input Carry bit 2-bit field specifying compare mode On-chip RAM configuration control bit Data memory address field...
Page 136: Instruction Set Summary
4.2.2 Instruction Set Summary Table 4–4 shows the instruction set summary for the TMS320C2x processor, which is a superset of the TMS320C1x instruction set. Included in the instruc- tion set are four special groups of instructions to improve overall processor throughput and ease of use.
Page 137 Instruction Set Table 4–4. Instruction Set Summary ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS Mnemonic and Description Words 16-Bit Opcode Absolute value of accumulator 1100 1110 0001 1011 Add to accumulator with shift 0000 SSSS MDDD DDDD ADDC Add to accumulator with carry 0100 0011 MDDD DDDD...
Page 138 Instruction Set Table 4–4. Instruction Set Summary (Continued) AUXILIARY REGISTERS AND DATA PAGE POINTER INSTRUCTIONS Mnemonic and Description Words 16-Bit Opcode ADRK Add to auxiliary register short immediate 0111 1110 KKKK KKKK CMPR Compare auxiliary register with auxiliary 1100 1110 0101 00KK register AR0 Load auxiliary register...
Page 139 Instruction Set Table 4–4. Instruction Set Summary (Continued) BRANCH/CALL INSTRUCTIONS Mnemonic and Description Words 16-Bit Opcode I/O AND DATA MEMORY OPERATIONS Branch unconditionally 1111 1111 1DDD DDDD BACC Branch to address specified by accumulator 1100 1110 0010 0101 BANZ Branch on auxiliary register not zero 1111 1011 1DDD DDDD...
Page 140 Instruction Set Table 4–4. Instruction Set Summary (Continued) CONTROL INSTRUCTIONS Mnemonic and Description Words 16-Bit Opcode Test bit 1001 BBBB MDDD DDDD BITT Test bit specified by T register 0101 0111 MDDD DDDD CNFD † Configure block as data memory 1100 1110 0000 0100...
Page 141 Individual Instruction Descriptions Individual Instruction Descriptions Each instruction in the instruction set summary is described in the following pages. Instructions are listed in alphabetical order. Information, such as as- sembler syntax, operands, operation, encoding, description, words, cycles, and examples, is provided for each instruction. An example instruction is pro- vided to familiarize you with the special format used and to explain its content.
Page 142 EXAMPLE Example Instructions Syntax Direct: [ label ] EXAMPLE dma [, shift ] Indirect: [ label ] EXAMPLE {ind} [, shift [ next ARP ]] Immediate: [ label ] EXAMPLE [ constant ] Each instruction begins with an assembler syntax expression. The optional comment field that concludes the syntax is not included in the syntax expres- sion.
Page 143 PR/DE Cycle Timings for a Repeat Execution The table shows the number of cycles required for a given TMS320C2x instruction to execute in a given memory configuration when executed as a single instruction or in the repeat mode. The column headings in the tables in-...
Page 144 T is the access time, in nanoseconds, (maximum) required by the TMS320C2x for an external memory access to be made with no wait states. T is the memory device access time, and T is the clock period (4/crystal frequency).
Page 145 EXAMPLE Example Instructions Example DAT1,3 ;(DP = 10) ;If current auxiliary register contains 1281. Before Instruction After Instruction Data Data Memory Memory 1281 1281 The sample code presented in the above format shows the effect of the code on memory and/or registers. The use of the carry bit (C) provided on the TMS320C25 is shown in the small box.
Page 146 ABS of 80000000h is 80000000h. In the overflow mode, the ABS of 80000000h is 7FFFFFFFh. In either case, the OV status bit is set. The carry bit (C) on the TMS320C2x is always reset to zero by the execution of this instruction.
Page 147 Absolute Value of Accumulator Example Before Instruction After Instruction 1234h 1234h 0FFFFFFFFh Assembly Language Instructions 4-24...
Page 148 Add to Accumulator With Shift Syntax Direct: [ label ] dma [, shift ] Indirect: [ label ] {ind} [, shift [, next ARP ]] Operands next ARP shift 15 (defaults to 0) Execution (PC) + 1 shift (ACC) + [(dma) x 2 If SXM = 1: Then (dma) is sign-extended.
Page 149 Add to Accumulator With Shift Example ADD DAT1,3 ;(DP = 10) ADD *,3 ;If current auxiliary register contains 1281. Before Instruction After Instruction Data Data Memory Memory 1281 1281 Assembly Language Instructions 4-26...
Page 150 ADDC Add to Accumulator With Carry Syntax Direct: [ label ] ADDC dma Indirect: [ label ] ADDC {ind} [, next ARP ] Operands dma 127 next ARP Execution (PC) + 1 (ACC) + (dma) + (C) Affects OV and C; affected by OVM. Encoding Direct: Data Memory Address...
Page 151 ADDC Add to Accumulator With Carry Example 2 ADDC DAT5 ;(DP = 8) ADDC * ;If current auxiliary register contains 1029. Before Instruction After Instruction Data Data Memory Memory 1029 1029 0FFFFFFFFh Assembly Language Instructions 4-28...
Page 152 (bits 31 through 16). Low-order bits are unaffected by ADDH. The carry bit (C) on the TMS320C2x is set if the result of the addition generates a carry; otherwise, C is unaffected. The carry bit can only be set, not reset, by the ADDH instruction.
Page 153 ADDH Add to High Accumulator Example ADDH DAT5 ;(DP = 8) ADDH * ;If current auxiliary register contains 1029. Before Instruction After Instruction Data Data Memory Memory 1029 1029 40013h Assembly Language Instructions 4-30...
Page 154 ADDK Add to Accumulator Short Immediate Syntax [ label ] ADDK constant Operands constant Execution (PC) + 1 (ACC) + 8-bit positive constant Affects OVM and C; affected by OVM. Not affected by SXM. Encoding 8-Bit constant Description The 8-bit immediate value is added, right-justified, to the accumulator with the result replacing the accumulator contents.
Page 155 ADDS Add to Accumulator With Sign-Extension Suppressed Syntax Direct: [ label ] ADDS dma Indirect: [ label ] ADDS {ind}[, next ARP ] Operands dma 127 next ARP Execution (PC) + 1 (ACC) + (dma) (dma) is a 16-bit unsigned number. Affects OV;...
Page 156 ADDS Add to Accumulator With Sign-Extension Suppressed Example ADDS DAT11 ;(DP = 6) ADDS * ;If current auxiliary register contains 779. Before Instruction After Instruction Data Data 0F006h 0F006h Memory Memory 0F009h 4-33...
Page 157 ADDT Add to Accumulator With Shift Specified by T Register Syntax Direct: [ label ] ADDT dma Indirect: [ label ] ADDT {ind} [, next ARP ] Operands next ARP Execution (PC) + 1 T register(3–0) (ACC) + [(dma) (ACC) If SXM = 1: Then (dma) is sign-extended.
Page 158 ADDT Add to Accumulator With Shift Specified by T Register Example ADDT DAT127 ;(DP = 4) ADDT * ;If current auxiliary register contains 639. Before Instruction After Instruction Data Data Memory Memory 0FF94h 0FF94h 0F715h 0F7A5h 4-35...
Page 159 ADLK Add to Accumulator Long Immediate With Shift Syntax [ label ] ADLK constant [, shift ] Operands 16-bit constant shift 15 (defaults to 0) Execution (PC) + 2 shift (ACC) + [ constant x 2 If SXM = 1: Then –32768 constant 32767.
Page 160 ADRK Add to Auxiliary Register Short Immediate Syntax [ label ] ADRK constant Operands constant Execution (PC) + 1 AR(ARP) + 8-bit positive constant AR(ARP) Encoding Direct: 8-Bit constant Description The 8-bit immediate value is added, right-justified, to the currently selected auxiliary register with the result replacing the auxiliary register contents.
Page 161 AND With Accumulator Syntax Direct: [ label ] Indirect: [ label ] {ind} [, next ARP ] Operands dma 127 next ARP Execution (PC) + 1 (ACC(15–0)) AND (dma) ACC(15–0) ACC(31–16) Not affected by SXM. Encoding Direct: Data Memory Address Indirect: See Section 4.1 Description...
Page 162 AND With Accumulator Example AND DAT16 ;(DP = 4) AND * ;If current auxiliary register contains 528. Before Instruction After Instruction Data Data 0FFh 0FFh Memory Memory 12345678h 00000078h 4-39...
Page 163 ANDK AND Immediate With Accumulator With Shift Syntax [ label ] ANDK constant [, shift ] Operands 16-bit constant shift 15 (defaults to 0) Execution (PC) + 2 shift (ACC(30–0)) AND [( constant ACC(30–0) ACC(31) and all other bit positions unoccupied by shifted constant. Not affected by SXM.
Page 164 APAC Add P Register to Accumulator Syntax [ label ] APAC Operands None Execution (PC) + 1 (ACC) + ( shifted P register) Affects OV; affected by PM and OVM. Affects C. Not affected by SXM. Encoding Description The contents of the P register are shifted as defined by the PM status bits and added to the contents of the accumulator.
Page 165 Branch Unconditionally Syntax [ label ] pma [,{ind} [, next ARP ] ] Operands 65535 next ARP Execution Modify AR(ARP) and ARP as specified. Encoding See Section 4.1 Program Memory Address Description The current auxiliary register and ARP are modified as specified, and control passes to the designated program memory address (pma).
Page 166 BACC Branch to Address Specified by Accumulator Syntax [ label ] BACC Operands None Execution (ACC(15–0)) Encoding Description The branch uses the lower half of the accumulator (bits 15 – 0) for the branch address. Words Cycles Cycle Timings for a Single Instruction PI/DI PI/DE PE/DI...
Page 167 BANZ Branch on Auxiliary Register Not Zero Syntax [ label ] BANZ pma [,{ind} [, next ARP ]] Operands 65535 next ARP Execution f AR (ARP) Then pma Else (PC) + 2 Modify AR (ARP) as specified. Encoding See Section 4.1 Program Memory Address Description Control is passed to the designated program memory address (pma) if the cur-...
Page 168 BANZ Branch on Auxiliary Register Not Zero Example 1 BANZ PRG35, * — Before Instruction After Instruction 0FFFFh Example 2 BANZ PRG64, * + Before Instruction After Instruction 0FFFFh 117h 119h 117h Note: BANZ is designed for loop control using the auxiliary registers as loop count- ers.
Page 169 BBNZ Branch on TC Bit Not Equal to Zero Syntax [ label ] BBNZ pma [,{ind} [, next ARP ]] Operands 65536 next ARP Execution If test/control (TC) status = 1: Then pma Else (PC) + 2 Modify AR (ARP) and ARP as specified. Affected by TC bit Encoding See Section 4.1...
Page 170 Branch on TC Bit Equal to Zero Syntax [ label ] pma [,{ind} [, next ARP ]] Operands 65536 next ARP Execution If test/control (TC) status bit = 0: Then pma Else (PC) + 2 Modify AR (ARP) and ARP as specified. Affected by TC bit Encoding See Section 4.1...
Page 171 Branch on Carry Syntax [ label ] [,{ind} [, next ARP ]] Operands 65536 next ARP Execution If carry bit C = 1: Then pma Else (PC) + 2 Modify AR (ARP) and ARP as specified. Affected by TC bit Encoding See Section 4.1 Program Memory Address...
Page 172 BGEZ Branch if Accumulator Greater Than or Equal to Zero Syntax [ label ] BGEZ pma [ , {ind} [ , next ARP ]] Operands 65536 next ARP Execution If (ACC) Then pma Else (PC) + 2 Modify AR (ARP) and ARP as specified. Encoding See Section 4.1 Program Memory Address...
Page 173 Branch if Accumulator Greater Than Zero Syntax [ label ] [ , {ind} [ , next ARP ] ] Operands 65536 next ARP If (ACC) > 0: Execution Then pma Else (PC) + 2 Modify AR (ARP) and ARP as specified. Encoding See Section 4.1 Program Memory Address...
Page 174 BIOZ Branch on I/O Status Equal to Zero Syntax [ label ] BIOZ [ , {ind} [ , next ARP ] ] Operands 65536 next ARP Execution If BIO = 0: Then pma Else (PC) + 2 Modify AR (ARP) and ARP as specified. Encoding See Section 4.1 Program Memory Address...
Page 175 Test Bit Syntax Direct: [ label ] BIT dma , bit code Indirect : [ label ] BIT {ind} , bit code [, next ARP ] Operands next ARP bit code Execution (PC) + (dma bit at bit address (15-bit code) ) Affects TC.
Page 176 Test Bit Cycle Timings for a Single Instruction PI/DI PI/DE PE/DI PE/DE PR/DI PR/DE 2+d+p Cycle Timings for a Repeat Execution 1+n+nd 1+n+nd+p 1+n+nd Example 0h, 8h ;(DP = 488) ;If current auxiliary register contains 0F400h. Before Instruction After Instruction Data Data Memory...
Page 177 BITT Test Bit Specified by T Register Syntax Direct: [ label ] BITT Indirect: [ label ] BITT {ind} [, next ARP ] Operands dma 127 next ARP Execution (PC) + 1 (dma bit at bit address (15–T register(3–0) )) Affects TC.
Page 178 BITT Test Bit Specified by T Register Cycle Timings for a Single Instruction PI/DI PI/DE PE/DI PE/DE PR/DI PR/DE 2+d+p Cycle Timings for a Repeat Execution 1+n+nd 1+n+nd+p 1+n+nd Example BITT ;Value in T register points to bit 14 of ;data word (DP = 240).
Page 179 BLEZ Branch if Accumulator Less Than or Equal to Zero Syntax [ label ] BLEZ pma [,{ind} [, next ARP ]] Operands 65535 next ARP Execution If (ACC) Then pma Else (PC) + 2 Modify AR(ARP) and ARP as specified. Encoding See Section 4.1 Program Memory Address...
Page 180 BLKD Block Move From Data Memory to Data Memory Syntax Direct: [ label ] BLKD dma1 , dma2 Indirect: [ label ] BLKD dma1 ,{ind} [, next ARP ] Operands dma1 65535 dma2 127 next Execution (PC) + 2 (PFC) dma1 If (repeat counter) Then (dma1, addressed by PFC)
Page 181 BLKD Block Move From Data Memory to Data Memory Encoding Direct: Data Memory Address Data Memory Address 1 Indirect: See Section 4.1 Data Memory Address 1 Description Consecutive memory words are moved from a source data memory block to a destination data memory block. The starting address (lowest) of the source block is defined by the second word of the instruction.
Page 182 BLKD Block Move From Data Memory to Data Memory Cycle Timings for a Single Instruction PI/DI PI/DE PE/DI PE/DE PR/DI PR/DE Source data in on-chip RAM: 3+2p 3+d+2p Source data in external memory: 4+2d 4+d+2p 4+2d+2p 4+2d Cycle Timings for a Repeat Execution Source data in on-chip RAM: 2+n+nd 2+n+2p...
Page 183 BLKP Block Move From Program Memory to Data Memory Syntax Direct: [ label ] BLKP pma , dma Indirect: [ label ] BLKP pma ,{ind}[, next ARP ] Operands 65535 dma 127 next ARP Execution (PC) + 2 (PFC) If (repeat counter) Then (pma, addressed by PFC) dma, Modify AR(ARP) and ARP as specified,...
Page 184 BLKP Block Move From Program Memory to Data Memory The PC points to the instruction following BLKP after execution. Interrupts are inhibited during a BLKP operation. If the MP/MC pin on the TMS320C25 is low at the time of execution of this instruction and the program memory address used is less than 4096, an on- chip ROM location will be read.
Page 185 BLKP Block Move From Program Memory to Data Memory Example RPTK BLKP 65120,*+ ;If current auxiliary register contains 2048. Before Instruction After Instruction Data Data 0A089h 0A089h Memory Memory 65120 65120 Data Data 2DCEh 2DCEh Memory Memory 65121 65121 Data Data 3A9Fh 3A9Fh...
Page 186 Branch if Accumulator Less Than Zero Syntax [ label ] [,{ind} [, next ARP ]] Operands 65535 next ARP Execution If (ACC) < 0: Then pma Else (PC) + 2 Modify AR(ARP) and ARP as specified. Encoding See Section 4.1 Program Memory Address Description The current auxiliary register and ARP are modified as specified.
Page 187 Branch on No Carry Syntax [ label ] [,{ind} [, next ARP ]] Operands 65535 next ARP Execution If carry bit C = 0: Then pma Else (PC) + 2 Modify AR(ARP) and ARP as specified. Affected by C. Encoding See Section 4.1 Program Memory Address Description...
Page 188 Branch if No Overflow Syntax [ label ] [,{ind} [, next ARP ]] Operands 65535 next ARP Execution If overflow OV status bit = 0: Then pma Else (PC) + 2 PC and 0 Modify AR(ARP) and ARP as specified. Affects OV;...
Page 189 Branch if Accumulator Not Equal to Zero Syntax [ label ] [,{ind} [, next ARP ]] Operands 65535 next ARP Execution If (ACC) Then pma Else (PC) + 2 Modify AR(ARP) and ARP as specified. Encoding See Section 4.1 Program Memory Address Description The current auxiliary register and ARP are modified as specified.
Page 190 Branch on Overflow Syntax [ label ] [,{ind} [, next ARP ]] Operands 65535 next ARP Execution If overflow (OV) status bit = 1: Then pma PC and 0 Else (PC) + 2 Modify AR(ARP) and ARP as specified. Affects OV; affected by OV. Encoding See Section 4.1 Program Memory Address...
Page 191 Branch if Accumulator Equals Zero Syntax [ label ] [,{ind} [, next ARP ]] Operands 65535 next ARP Execution If (ACC) = 0: Then pma Else (PC) + 2 Modify AR(ARP) and ARP as specified. Encoding See Section 4.1 Program Memory Address Description The current auxiliary register and ARP are modified as specified.
Page 192 CALA Call Subroutine Indirect Syntax [ label ] CALA Operands None Execution (PC) + 1 (ACC(15–0)) Encoding Description The current program counter is incremented and pushed onto the top of the stack. Then, the contents of the lower half of the accumulator are loaded into the PC.
Page 193 CALA Call Subroutine Indirect Example CALA Before Instruction After Instruction Stack Stack Assembly Language Instructions 4-70...
Page 194 CALL Call Subroutine Syntax [ label ] CALL [,{ind} [, next ARP ]] Operands 65535 next ARP Execution (PC) + 2 Encoding See Section 4.1 Program Memory Address Description The current auxiliary register and ARP are modified as specified, and the PC (program counter) is incremented by two and pushed onto the top of the stack.
Page 195 CALL Call Subroutine Example CALL PRG109 Before Instruction After Instruction Stack Stack Assembly Language Instructions 4-72...
Page 196 CMPL Complement Accumulator Syntax [ label ] CMPL Operands None Execution (PC) + 1 (ACC) Encoding Description The contents of the accumulator are replaced with its logical inversion (1s complement). Words Cycles Cycle Timings for a Single Instruction PI/DI PI/DE PE/DI PE/DE PR/DI...
Page 197 CMPR Compare Auxiliary Register With Auxiliary Register AR0 Syntax [ label ] CMPR constant Operands Execution (PC) + 1 Compare AR(ARP) to AR0, placing result in TC bit of status register ST1. Affects TC. Not affected by SXM; does not affect SXM. Encoding Description The CMPR instruction performs the following comparisons dependent on the...
Page 198 CNFD Configure Block as Data Memory Syntax [ label ] CNFD Operands None Execution (PC) + 1 RAM configuration control (CNF) status bit Affects CNF. Encoding Description On-chip RAM block 0 is configured as data memory. The block is mapped to locations 512 through 767 in data memory.
Page 199 CNFP Configure Block as Program Memory Syntax [ label ] CNFP Operands None Execution (PC) + 1 RAM configuration control (CNF) status bit Affects CNF. Encoding Description On-chip RAM block 0 is configured as program memory. The block is mapped to locations 65280 through 65535 in program memory space.
Page 200 CONF Configure Blocks as Data/Program Memory (TMS320C26 Only) Syntax [ label ] CONF constant Operands constant Execution (PC) + 1 Constant program/data memory configuration mode status bits Encoding 1 CNF1 CNF0 Description The two low-order CNF bits of the instruction word are copied into the CNF0 and CNF1 field of status register ST1.
Page 201 DINT Disable Interrupt Syntax [ label ] DINT Operands None Execution (PC) + 1 interrupt mode (INTM) status bit Affects INTM. Encoding Description The interrupt mode (INTM) status bit is set to logic 1. Maskable interrupts are disabled immediately after the DINT instruction executes. Note that the LST instruction does not affect INTM.
Page 202 DMOV Data Move in Data Memory Syntax Direct: [ label ] DMOV dma Indirect: [ label ] DMOV {ind} [,<next ARP>] Operands next ARP Execution (PC) + 1 (dma) dma + 1 Affected by CNF. Encoding Direct: Data Memory Address Indirect: See Section 4.1 Description...
Page 203 DMOV Data Move in Data Memory Example DMOV DAT8 ;(DP=4) DMOV ;If current auxiliary register contains 520. Before Instruction After Instruction Data Data Memory Memory Data Data Memory Memory Assembly Language Instructions 4-80...
Page 204 EINT Enable Interrupt Syntax [ label ] EINT Operands None Execution (PC) + 1 interrupt-mode (INTM) status bit Affects INTM. Encoding Description The interrupt-mode flag (INTM) in the status register is cleared to logic 0. Maskable interrupts are enabled after the instruction following EINT executes. This allows an interrupt service routine to re-enable interrupts and execute a RET instruction before any other pending interrupts are processed.
Page 205 FORT Format Serial Port Registers Syntax [ label ] FORT constant Operands Constant = 0 or 1 Execution (PC) + 1 Constant format (FO) status bit Affects FO. Encoding Description The format (FO) status bit is loaded by the instruction with the LSB specified in the instruction.
Page 206 IDLE Idle Until Interrupt Syntax [ label ] IDLE Operands None Execution TMS320C25: (PC) + 1 interrupt mode (INTM) status bit Affects INTM. Encoding Description The IDLE instruction forces the program being executed to wait until an inter- rupt or reset occurs. The PC is incremented only once, and the device remains in an idle state until interrupted.
Page 207 Input Data From Port Syntax Direct: [ label ] dma , PA Indirect: [ label ] IN {ind}, PA [, next ARP ] Operands dma 127 next ARP port address PA Execution (PC) + 1 Port address address bus A3–A0 address bus A15–A4 Data bus D15–D0 Encoding...
Page 208 Load Accumulator With Shift Syntax Direct: [ label ] dma [, shift ] Indirect : [ label ] {ind} [, shift [, next ARP ]] Operands next ARP shift 15 (defaults to 0) Execution (PC) + 1 shift (dma) x 2 If SXM = 1: Then (dma) is sign-extended.
Page 209 LACK Load Accumulator Immediate Short Syntax [ label ] LACK constant Operands constant Execution (PC) + 1 8-bit positive constant Not affected by SXM. Encoding 8-Bit Constant Description The 8-bit constant is loaded into the accumulator right-justified. The upper 24 bits of the accumulator are zeroed (that is, sign extension is suppressed).
Page 210 LACT Load Accumulator With Shift Specified by T Register Syntax Direct: [ label ] LACT dma Indirect: [ label ] LACT {ind} [, next ARP ] Operands next ARP Execution (PC) + 1 (dma) x 2 register(3–0) If SXM = 1: Then (dma) is sign-extended.
Page 211 LACT Load Accumulator With Shift Specified by T Register Example LACT DAT1 ;(DP = 6) LACT ;If current auxiliary register contains 769. Before Instruction After Instruction Data Data 1376h 1376h Memory Memory 98F7EC83h 13760h 3014h 3014h Assembly Language Instructions 4-88...
Page 212 LALK Load Accumulator Long Immediate With Shift Syntax [ label ] LALK constant [, shift ] Operands 16-bit constant shift 15 (defaults to 0) Execution (PC) + 2 shift Constant x 2 If SXM = 1: Then –32768 constant 32767. If SXM = 0: Then 0 constant...
Page 213 Load Auxiliary Register Syntax Direct: [ label ] AR dma Indirect:[ label ] AR , {ind} [, next ARP ] Operands auxiliary register AR next ARP Execution (PC) + 1 (dma) auxiliary register AR Encoding Direct: Data Memory Address Indirect: See Section 4.1 Description The contents of the specified data memory address are loaded into the desig-...
Page 214 Load Auxiliary Register Example 1 AR0,DAT10 ;(DP = 4) Before Instruction After Instruction Data Data Memory Memory Example 2 LARP AR4,*– Before Instruction After Instruction Data Data Memory Memory 617h Note: LAR, in the indirect addressing mode, ignores any AR modifications if the AR specified by the instruction is the same as that pointed to by the ARP.
Page 215 LARK Load Auxiliary Register Immediate Short Syntax [ label ] LARK AR , constant Operands constant auxiliary register AR Execution (PC) + 1 8-bit constant auxiliary register AR Encoding 8-Bit Constant Description The 8-bit positive constant is loaded into the designated auxiliary register (AR) right-justified and zero-filled (that is, sign-extension suppressed).
Page 216 LARP Load Auxiliary Register Pointer Syntax [ label ] LARP constant Operands constant Execution (PC) + 1 (ARP) Constant Affects ARP and ARB. Encoding Description The auxiliary register pointer is loaded with the contents of the three LSBs of the instruction (a 3-bit constant identifying the desired auxiliary register). The old ARP is copied to the ARB field of status register ST1.
Page 217 Load Data Memory Page Pointer Syntax Direct: [ label ] Indirect: [ label ] {ind} [, next ARP ] Operands dma 127 next ARP Execution (PC) + 1 Nine LSBs of (dma) data page pointer register (DP) status bits Affects DP. Encoding Direct: Data Memory Address...
Page 218 LDPK Load Data Memory Page Pointer Immediate Syntax [ label ] LDPK constant Operands constant Execution (PC) + 1 Constant data memory page pointer (DP) status bits Affects DP. Encoding Description The DP (data memory page pointer) register is loaded with a 9-bit constant. The DP and 7-bit data memory address are concatenated to form 16-bit direct data memory addresses.
Page 219 Load High P Register Syntax Direct: [ label ] Indirect: [ label ] {ind} [, next ARP ] Operands dma 127 next ARP Execution (PC) + 1 (dma) P register (31 – 16) Encoding Direct: Data Memory Address Indirect: See Section 4.1 Description The P register high-order bits are loaded with the contents of data memory.
Page 220 LRLK Load Auxiliary Register Long Immediate Syntax [ label ] LRLK AR , constant Operands auxiliary register constant 65535 Execution (PC) + 2 Constant Not affected by SXM; does not affect SXM. Encoding 16-Bit Constant Description The 16-bit immediate value is loaded into the auxiliary register specified by the AR field.
Page 221 Load Status Register ST0 Syntax Direct: [ label ] Indirect: [ label ] {ind} [, next ARP ] Operands next ARP Execution (PC) + 1 (dma) status register ST0 Affects ARP, OV, OVM, and DP. Does not affect INTM or ARB. Encoding Direct: Data Memory Address...
Page 222 Load Status Register ST0 Example 1 LARP ;The data memory word addressed by the contents ;of auxiliary register AR0 is loaded into ;status register ST0, except for the INTM bit. ;Note that even though a next ARP value is ;specified, that value is ignored, and even ;though a new ARP is loaded, the old ARP is not ;loaded into ARB.
Page 223 LST1 Load Status Register ST1 Syntax Direct: [ label ] LST1 Indirect: [ label ] LST1 {ind} [, next ARP ] Operands next ARP Execution (PC) + 1 (dma) status register ST1 (ARB) Affects ARP, ARB, CNF, TC, SXM, XF, FO, TXM, and PM. Affects C, HM, and FSM (TMS320C25) Encoding Direct:...
Page 224 LST1 Load Status Register ST1 Cycles Cycle Timings for a Single Instruction PI/DI PI/DE PE/DI PE/DE PR/DI PR/DE 2+d+p Cycle Timings for a Repeat Execution 2n+nd 2n+nd+p 2n+nd Example 1 LARP LST1 *– ;The data memory word addressed by the contents ;of auxiliary register AR3 replaces the status ;bits of status register ST1, and AR3 is ;decremented.
Page 225 LST1 Load Status Register ST1 Example 4 LARP ;(AR4 = 3FEh) LST1 *–,1 Before Instruction After Instruction 3FEh 3FDh Data Data 6190h 6190h Memory Memory 1022 1022 0FE04h 7E04h 0593h 6190h Assembly Language Instructions 4-102...
Page 226 Load T Register Syntax Direct: [ label ] LT dma Indirect: [ label ] LT {ind} [, next ARP ] Operands next ARP Execution (PC) + 1 (dma) T register Encoding Direct: Data Memory Address Indirect: See Section 4.1 Description The T register is loaded with the contents of the specified data memory ad- dress (dma).
Page 227 Load T Register and Accumulate Previous Product Syntax Direct: [ label ] Indirect: [ label ] {ind} [, next ARP ] Operands next ARP Execution (PC) + 1 (dma) T register (ACC) + (shifted P register) Affects OV; affected by OVM and PM. Affects C.
Page 228 Load T Register and Accumulate Previous Product Example DAT36 ;(DP = 6, PM = 0) ;If current auxiliary register contains 804. Before Instruction After Instruction Data Data Memory Memory 4-105...
Page 229 Load T Register, Accumulate Previous Product, and Move Data Syntax Direct: [ label ] Indirect: [ label ] {ind} [, next ARP ] Operands next ARP Execution (PC) + 1 (dma) T register (dma) dma + 1 (ACC) + (shifted P register) Affects OV;...
Page 230 Load T Register, Accumulate Previous Product, and Move Data Example DAT126 ;(DP = 7, PM = 0) ;If current auxiliary register contains 1022. Before Instruction After Instruction Data Data Memory Memory 1022 1022 Data Data Memory Memory 1023 1023 4-107...
Page 231 Load T Register and Store P Register in Accumulator Syntax Direct: [ label ] Indirect: [ label ] {ind} [, next ARP ] Operands next ARP Execution (PC) + 1 (dma) T register (shifted P register) Affected by PM. Encoding Direct: Data Memory Address Indirect:...
Page 232 Load T Register and Subtract Previous Product Syntax Direct: [ label ] Indirect: [ label ] [ind] [, next ARP ] Operands next ARP Execution (PC) + 1 (dma) T register (ACC) – (shifted P register) Affects OV; affected by PM and OVM. Affects C.
Page 233 Load T Register and Subtract Previous Product Example DAT36 ;(DP = 6, PM = 0) LTS * ;If current auxiliary register contains 804. Before Instruction After Instruction Data Data Memory Memory 0FFFFFFF6h Assembly Language Instructions 4-110...
Page 234 Multiply and Accumulate Syntax Direct: [ label ] pma , dma Indirect: [ label ] pma , {ind} [, next ARP ] Operands 65535 dma 127 next ARP Execution TMS320C25: (PC) + 2 (PFC) (pma) If (repeat counter) Then (ACC) + (shifted P register) ACC, (dma) T register,...
Page 235 Multiply and Accumulate When the MAC instruction is repeated, the program memory address con- tained in the PC/PFC is incremented by one during its operation. This enables accessing a series of operands in memory. MAC is useful for long sum-of- products operations, since MAC becomes a single-cycle instruction once the RPT pipeline is started.
Page 236 Multiply and Accumulate Example ;Select a shift-right-by-6 mode on PR output. ;on PR output. CNFP ;Configure block B0 as program memory ;(0FFXXh). LARP ;Use AR1 to address block B1. LRLK 1,768 ;Point to lowest location in RAM block B1 RPTK ;Compute 256 sum-of-product operations.
Page 237 MACD Multiply and Accumulate With Data Move Syntax Direct: [ label ] MACD pma , dma Indirect: [ label ] MACD pma , {ind} [, next ARP ] Operands 65535 next ARP Execution TMS320C25: (PC) + 2 (PFC) (pma) If (repeat counter) Then (ACC) + (shifted P register) ACC, (dma)
Page 238 MACD Multiply and Accumulate With Data Move to address B0 program RAM, and the upper six bits of dma should be set to 0 to address a location below 1024. When used in the direct addressing mode, the dma cannot be modified during repetition of the instruction. If MACD ad- dresses one of the memory-mapped registers or external memory as a data memory location, the effect of the instruction will be that of a MAC instruction (see the DMOV instruction description).
Page 239 MACD Multiply and Accumulate With Data Move Example ;Select no shift mode on PR output. SOVM ;Set overflow mode. CNFP ;Configure block program memory ;(0FFXXh). LARP ;Use AR3 to address block B1. LRLK 3,1023 ;Point to highest location in RAM block B1. RPTK ;Compute sample...
Page 240 Modify Auxiliary Register Syntax Direct: [ label ] Indirect: [ label ] {ind} [, next ARP ] Operands dma 127 next ARP Execution (PC) + 1 Modifies ARP, AR(ARP) as specified by the indirect addressing field (acts as a NOP in direct addressing). Encoding Direct: Data Memory Address...
Page 241 Modify Auxiliary Register Example 1 ;Load the ARP with 1. Before Instruction After Instruction Example 2 *– ;Decrement current auxiliary register (in this ;case, AR1). Before Instruction After Instruction Example 3 *+,5 ;Increment current auxiliary register (AR1) and ;load ARP with 5. Before Instruction After Instruction Assembly Language Instructions...
Page 242 Multiply Syntax Direct: [ label ] Indirect: [ label ] {ind} [, next ARP ] Operands next ARP Execution (PC) + 1 (T register) (dma) P register Encoding Direct: Data Memory Address Indirect: See Section 4.1 Description The contents of the T register are multiplied by the contents of the addressed data memory location.
Page 243 MPYA Multiply and Accumulate Previous Product Syntax Direct: [ label ] MPYA dma Indirect: [ label ] MPYA {ind} [, next ARP ] Operands next ARP Execution (PC) + 1 (ACC) + (shifted P register) (T register) (dma) P register Affects C and OV;...
Page 244 MPYK Multiply Immediate Syntax [ label ] MPYK constant Operands –4096 constant 4095 –2 constant – 1 Execution (PC) + 1 (T register) constant P register Not affected by SXM. Encoding 13-Bit Constant Description The contents of the T register are multiplied by the signed, 13-bit constant. The result is loaded into the P register.
Page 245 MPYS Multiply and Subtract Previous Product Syntax Direct: [ label ] MPYS dma Indirect: [ label ] MPYS {ind} [, next ARP ] Operands next ARP Execution (PC) + 1 (ACC) – (shifted P register) (T register) (dma) P register Affects C and OV;...
Page 246 MPYU Multiply Unsigned Syntax Direct: [ label ] MPYU dma Indirect : [ label ] MPYU {ind} [, next ARP ] Operands next ARP Execution (PC) + 1 Unsigned (T register) unsigned (dma) P register Encoding Direct: Data Memory Address Indirect: See Section 4.1 Description...
Page 247 MPYU Multiply Unsigned Example MPYU DAT16 ;(DP = 4) MPYU ;If current auxiliary register contains 528 Before Instruction After Instruction Data Data 0FFFFh 0FFFFh Memory Memory 0FFFFh 0FFFFh 0FFFE0001h Assembly Language Instructions 4-124...
Page 248 OVM = 1, the accumulator contents are replaced with 7FFFFFFFh. If OVM = 0, the result is 80000000h. The carry bit C on the TMS320C2x is reset to zero by this instruction for all nonzero values of the accumulator and is set to one if the accumulator equals zero.
Page 249 No Operation Syntax [ label ] Operands None Execution (PC) + 1 Encoding Description No operation is performed. The NOP instruction affects only the PC. NOP functions in the same manner as the MAR instruction in the direct addressing mode; NOP has the same opcode as MAR in the direct addressing mode with dma = 0.
Page 250 NORM Normalize Contents of Accumulator Syntax [ label ] NORM {ind} (TMS320C25) Operands None Execution TMS320C25: (PC) + 1 If (ACC) = 0: Then 1 Else, if (ACC(31)) XOR (ACC(30)) = 0: Then 0 (ACC) ACC, Modify AR(ARP) as specified; Else 1 Affects TC.
Page 251 NORM Normalize Contents of Accumulator Cycle Timings for a Single Instruction PI/DI PI/DE PE/DI PE/DE PR/DI PR/DE Cycle Timings for a Repeat Execution Example 1 31-Bit Normalization: LARP ;Use AR1 for exponent storage. LARK ;Clear out exponent counter. LOOP NORM *+ ;One bit is normalized.
Page 252 OR With Accumulator Syntax Direct: [ label ] Indirect: [ label ] {ind} [, next ARP ] Operands next ARP Execution (PC) + 1 (ACC(15–0)) OR dma ACC(15–0) (ACC(31–16)) ACC(31–16) Not affected by SXM. Encoding Direct: Data Memory Address Indirect: See Section 4.1 Description The low-order bits of the accumulator are ORed with the contents of the ad-...
Page 253 OR Immediate With Accumulator With Shift Syntax [ label ] constant [, shift ] Operands 16-bit constant shift 15 (defaults to 0) Execution (PC) + 2 shift (ACC(30–0)) OR [constant x 2 ACC(30–0) (ACC(31)) ACC(31) Not affected by SXM. Encoding Shift 16-Bit Constant Description...
Page 254 Output Data to Port Syntax Direct: [ label ] dma , PA Indirect: [ label ] {ind}, PA [, next ARP ] Operands next ARP port address PA Execution PC) + 1 Port address PA address bus A3 – A0 address bus A15 –...
Page 255 Load Accumulator With P Register Syntax [ label ] Operands None Execution PC) + 1 (shifted P register) Affected by PM. Encoding Description The contents of the P register are loaded into the accumulator, shifted as spe- cified by the PM status bits. Words Cycles Cycle Timings for a Single Instruction...
Page 256 The upper half of the accumulator is set to all zeros. The hardware stack is a last-in, first-out stack with eight (TMS320C2x) loca- tions. Any time a pop occurs, every stack value is copied to the next higher stack location, and the top value is removed from the stack.
Page 257 The value from the top of the stack is transferred into the data memory location specified by the instruction. The values are also popped in the lower seven locations (TMS320C2x) of the stack. The hardware stack is described in the previous instruction POP. The lowest stack location remains unaffected. No provision exists to check stack underflow.
Page 258 The value from the data memory location specified by the instruction is trans- ferred to the top of the stack. The values are also pushed down in the lower seven locations (TMS320C2x) of the stack, as described in the instruction PUSH. The lowest stack location is lost.
Page 259 The hardware stack is a last-in, first-out stack with eight locations (TMS320C2x). If more than eight pushes (due to CALA, CALL, PSHD, PUSH, or TRAP instructions) occur before a pop, the first data values written will be lost with each succeeding push.
Page 260 Reset Carry Bit Syntax [ label ] Operands None Execution (PC) + 1 carry bit C in status register ST1 Affects C. Encoding Description The carry bit C in status register ST1 is reset to logic zero. The carry bit may also be loaded directly by the LST1 and SC instructions.
Page 261 Return From Subroutine Syntax [ label ] Operands None Execution (TOS) Pop stack one level. Encoding Description The contents of the top stack register are copied into the program counter. The stack is then popped one level. RET is used with CALA and CALL for subrou- tines.
Page 262 RFSM Reset Serial Port Frame Synchronization Mode Syntax [ label ] RFSM Operands None Execution (PC) + 1 FSM status bit in status register ST1 Affects FSM. Encoding Description The RFSM status bit resets the FSM status bit to logic zero. In this mode, exter- nal FSR pulses are not required to initiate the receive operation for each word received, but rather only one FSR pulse is required to initiate a continuous mode of operation.
Page 263 Reset Hold Mode Syntax [ label ] Operands None Execution (PC) + 1 HM status bit in status register ST1 Affects HM. Encoding Description The RHM instruction clears internal execution when acknowledging an active HOLD (HM = 1). When HM = 0, the processor may continue execution out of internal memory but puts its external interface in a high-impedance state.
Page 264 Rotate Accumulator Left Syntax [ label ] Operands None Execution (PC) + 1 (ACC(31)) (ACC(30 – 0)) ACC(31 –1) (C, before ROL) ACC(0) Affects C. Not affected by SXM. Encoding Description The ROL instruction rotates the accumulator left one bit. The MSB is shifted into the carry bit, and the value of the carry bit from before the execution of the instruction is shifted into the LSB.
Page 265 Rotate Accumulator Right Syntax [ label ] Operands None Execution (PC) + 1 (ACC(0)) (ACC(31–1)) ACC(30–0) (C, before ROR) ACC(31) Affects C. Not affected by SXM. Encoding Description The ROR instruction rotates the accumulator right one bit. The LSB is shifted into the carry bit, and the value of the carry bit from before the execution of the instruction is shifted into the MSB.
Page 266 ROVM Reset Overflow Mode Syntax [ label ] ROVM Operands None Execution (PC) + 1 OVM status bit in status register ST0 Affects OVM. Encoding Description The OVM status bit is reset to logic zero, which disables the overflow mode. If an overflow occurs with OVM reset, the OV (overflow flag) is set, and the overflowed result is placed in the accumulator.
Page 267 Repeat Instructions as Specified by Data Memory Value Syntax Direct: [ label ] Indirect: [ label ] {ind} [, next ARP ] Operands next ARP Execution (PC) + 1 (dma(7–0)) RPTC Encoding Direct: Data Memory Address Indirect: See Section 4.1 Description The eight LSBs of the addressed data memory value are loaded into the repeat counter (RPTC).
Page 268 RPTK Repeat Instructions as Specified by Immediate Value Syntax [ label ] RPTK constant Operands constant Execution (PC) + 1 Constant RPTC Encoding 8–Bit Constant Description The 8-bit immediate value is loaded into the RPTC (repeat counter). This causes the following instruction to be executed one time more than the number loaded into the RPTC (provided that it is a repeatable instruction).
Page 269 RSXM Reset Sign-Extension Mode Syntax [ label ] RSXM Operands None Execution (PC) + 1 SXM sign-extension mode status bit Affects SXM. Encoding Description The RSXM instruction resets the SXM status bit to logic zero, which sup- presses sign-extension on shifted data memory values for the following arith- metic instructions: ADD, ADDT, ADLK, LAC, LACT, LALK, SBLK, SUB, and SUBT.
Page 270 Reset Test/Control Flag Syntax [ label ] Operands None Execution (PC) + 1 TC test/control flag in status register ST1 Affects TC. Encoding Description The TC (test/control) flag in status register ST1 is reset to logic zero. TC can also be loaded by the LST1 and STC instructions. Words Cycles Cycle Timings for a Single Instruction...
Page 271 RTXM Reset Serial Port Transmit Mode Syntax [ label ] RTXM Operands None Execution (PC) + 1 TXM transmit mode status bit Affects TXM mode bit. Encoding Description The RTXM instruction resets the TXM status bit, which configures the serial port transmit section in a mode where it is controlled by an FSX (external fram- ing pulse).
Page 272 Rest External Flag Syntax [ label ] Operands None Execution (PC) + 1 XF external flag pin and status bit Affects XF. Encoding Description The XF pin and XF status bit in status register ST1 are reset to logic zero. XF may also be loaded by the LST1 and SXF instructions.
Page 273 The SACH instruction copies the entire accumulator into a shifter, where it shifts the entire 32-bit number anywhere from 0 to 7 bits on the TMS320C2x. It then copies the upper 16 bits of the shifted value into data memory. The accu- mulator itself remains unaffected.
Page 274 The low-order bits of the accumulator are shifted left 0 to 7 bits on the TMS320C2x, as specified by the shift code, and stored in data memory. The low-order bits are filled with zeros, and the high-order bits are lost. The accu- mulator itself is unaffected.
Page 275 Store Auxiliary Register Syntax Direct: [ label ] AR , dma Indirect: [ label ] AR , {ind} [, next ARP ] Operands auxiliary register AR next ARP Execution (PC) + 1 (AR) Encoding Direct: Data Memory Address Indirect: See Section 4.1 Description The contents of the designated auxiliary register (AR) are stored in the ad- dressed data memory location.
Page 276 Store Auxiliary Register Example 1 AR0,DAT30 ;(DP = 6) AR0,* ;If current auxiliary register contains 798. Before Instruction After Instruction Data Data Memory Memory Example 2 LARP AR0,*0+ Before Instruction After Instruction 401h 802h Data Data Memory Memory 401h 1025 1025 4-153...
Page 277 SBLK Subtract From Accumulator Long Immediate With Shift Syntax [ label ] SBLK constant [, shift ] Operands 16-bit constant shift 15 (defaults to 0) Execution (PC) + 2 shift] (ACC) –[constant If SXM = 1: Then –32768 constant 32767. If SXM = 0: Then 0 constant...
Page 278 SBRK Subtract From Auxiliary Register Short Immediate Syntax [ label ] SBRK constant Operands constant Execution (PC) + 1 AR(ARP) – 8-bit positive constant AR(ARP) Encoding 8-Bit Constant Description The 8-bit immediate value is subtracted, right-justified, from the currently se- lected auxiliary register with the result replacing the auxiliary register contents.
Page 279 Set Carry Bit Syntax [ label ] Operands None Execution (PC) + 1 carry bit C in status register ST1 Affects C. Encoding Description The carry bit C in status register ST1 is set to logic one. The carry bit may also be loaded directly by the LST1 and RC instructions.
Page 280 The SFL instruction shifts the entire accumulator left one bit. The least signifi- cant bit is filled with a zero. On the TMS320C2x, the most significant bit is shifted into the carry bit (C). Note that SFL, unlike SFR, is unaffected by SXM.
Page 281 Shift Accumulator Right Syntax [ label ] Operands None Execution (PC) + 1 If SXM = 0: Then (ACC(0)) (ACC(31–1)) ACC (30–0) and 0 ACC(31) If SXM = 1: Then (ACC(0)) (ACC(31–1)) ACC(30–0) and (ACC(31)) ACC(31) Affects C. Affected by SXM bit. Encoding Description The SFR instruction shifts the accumulator right one bit.
Page 282 SFSM Set Serial Port Frame Synchronization Mode Syntax SFSM Operands None Execution (PC) + 1 FSM status bit in status register ST1 Affects FSM. Encoding Description The SFSM instruction sets the FSM status bit to logic one. In this mode, an external FSR pulse is required for a receive operation, and an external FSX pulse is required if TXM = 0.
Page 283 Set Hold Mode Syntax [ label ] Operands None Execution (PC) + 1 HM status bit in status register ST1 Affects HM. Encoding Description The SHM instruction halts internal execution when acknowledging an active HOLD (HM = 1). When HM = 0, the processor may continue execution out of internal memory but puts its external interface in a high-impedance state.
Page 284 SOVM Set Overflow Mode Syntax [ label ] SOVM Operands None Execution (PC) + 1 overflow mode (OVM) status bit Affects OVM. Encoding Description The OVM status bit is set to logic one, which enables the overflow (saturation) mode. If an overflow occurs with OVM set, the overflow flag OV is set, and the accumulator is set to the largest representable 32-bit positive (7FFFFFFFh) or negative (80000000h) number according to the direction of overflow.
Page 285 SPAC Subtract P Register From Accumulator Syntax [ label ] SPAC Operands None Execution PC) + 1 (ACC) – (shifted P register) Affects OV; affected by PM and OVM. Affects C. Not affected by SXM. Encoding Description The contents of the P register, shifted as defined by the PM status bits, are sub- tracted from the contents of the accumulator.
Page 286 Store High P Register Syntax Direct: [ label ] Indirect: [ label ] {ind} [, next ARP ] Operands next ARP Execution (PC) + 1 (PR shifter output (31–16)) Affected by PM. Encoding Direct: Data Memory Address Indirect: See Section 4.1 Description The high-order bits of the P register, shifted as specified by the PM bits, are stored in data memory.
Page 287 Store Low P Register Syntax Direct: [ label ] Indirect: [ label ] {ind} [, next ARP ] Operands next ARP Execution (PC) + 1 (PR shifter output (15–0)) Affected by PM. Encoding Direct: Data Memory Address Indirect: See Section 4.1 Description The low-order bits of the P register, shifted as specified by the PM bits, are stored in data memory.
Page 288 Set P Register Output Shift Mode Syntax [ label ] constant Operands constant Execution (PC) + 1 Constant product register shift mode (PM) status bits Affects PM. Encoding Description The two low-order bits of the instruction word are copied into the PM field of status register ST1.
Page 289 SQRA Square and Accumulate Previous Product Syntax Direct: [ label ] SQRA dma Indirect: [ label ] SQRA {ind} [, next ARP ] Operands next ARP Execution (PC) + 1 (ACC) + (shifted P register) (dma) T register (dma) (dma) P register Affects OV;...
Page 290 SQRS Square and Subtract Previous Product Syntax Direct: [ label ] SQRS dma Indirect: [ label ] SQRS {ind} [, next ARP ] Operands dma 127 next ARP Execution (PC) + 1 (ACC) – (shifted P register) (dma) T register (dma) (dma) P register...
Page 291 Store Status Register ST0 Syntax Direct: [ label ] Indirect: [ label ] {ind} [, next ARP ] Operands dma 127 next ARP Execution (PC) + 1 (status register ST0) Encoding Direct: Data Memory Address Indirect: See Section 4.1 Description Status register ST0 is stored in data memory.
Page 292 Store Status Register ST0 Cycle Timings for a Single Instruction PI/DI PI/DE PE/DI PE/DE PR/DI PR/DE 2+d+p Cycle Timings for a Repeat Execution n+nd 1+n+nd+p n+nd Example DAT96 ;(DP = don’t care) ;If current auxiliary register contains 96. Before Instruction After Instruction Status Status...
Page 293 TC (test/control), SXM (sign-extension mode), XF (external flag), FO (serial port format), TXM (transmit mode), and the PM (product regis- ter shift mode). ST1 on the TMS320C2x also contains the status bits: C (carry) bit, HM (hold mode), and FSM (frame synchronization mode). The bits loaded...
Page 294 SST1 Store Status Register ST1 Cycle Timings for a Single Instruction PI/DI PI/DE PE/DI PE/DE PR/DI PR/DE 2+d+p Cycle Timings for a Repeat Execution n+nd 1+n+nd+p n+nd Example SST1 DAT97 ;(DP = don’t care) SST1 ;If current auxiliary register contains 97. Before Instruction After Instruction Status...
Page 295 SSXM Set Sign-Extension Mode Syntax [ label ] SSXM Operands None Execution (PC) + 1 SXM status bit in status register ST1 Affects SXM. Encoding Description The SSXM instruction sets the SXM status bit to logic 1, which enables sign- extension on shifted data memory values for the following arithmetic instruc- tions: ADD, ADDT, ADLK, LAC, LACT, LALK, SBLK, SUB, and SUBT.
Page 296 Set Test/Control Flag Syntax [ label ] Operands None Execution (PC) + 1 TC test/control flag in status register ST1 Affects TC. Encoding Description The TC (test/control) flag in status register ST1 is set to logic one. TC may also be loaded by the LST1 and RTC instructions.
Page 297 STXM Set Serial Port Transmit Mode Syntax [ label ] STXM Operands None Execution (PC) + 1 TXM status bit in status register ST1 Affects TXM. Encoding Description The STXM instruction sets the TXM status bit to logic 1, which configures the serial port transmit section to a mode where the FSX pin behaves as an output.
Page 298 Subtract from Accumulator with Shift Syntax Direct: [ label ] dma [, shift ] Indirect: [ label ] {ind} [, shift [ next ARP ]] Operands next ARP shift 15 (defaults to 0) Execution (PC) + 1 shift (ACC) – [(dma) If SXM = 1: Then (dma) is sign-extended.
Page 299 SUBB Subtract from Accumulator with Borrow Syntax Direct: [ label ] SUBB dma Indirect : [ label ] SUBB {ind} [, next ARP ] Operands dma 127 next ARP Execution (PC) + 1 (ACC) – (dma) – (C) Affects C and OV; affected by OVM. Encoding Direct: Data Memory Address...
Page 300 SUBC Conditional Subtract Syntax Direct: [ label ] SUBC dma Indirect: [ label ] SUBC {ind} [, next ARP ] Operands dma 127 next ARP Execution (PC) + 1 (ACC) – [(dma) ALU output If ALU output Then (ALU output) 2 + 1 ACC;...
Page 301 SUBC Conditional Subtract Cycles Cycle Timings for a Single Instruction PI/DI PI/DE PE/DI PE/DE PR/DI PR/DE 2+d+p Cycle Timings for a Repeat Execution 1+n+nd 1+n+nd+p 1+n+nd Example RPTK SUBC DAT2 ;(DP = 4) RPTK SUBC ;If current auxiliary register contains 514. Before Instruction After Instruction Data...
Page 302 16 bits of the accumulator. The 16 low-order bits of the accumulator are unaffected. The result is stored in the accumulator. The carry bit C on the TMS320C2x is reset if the result of the subtraction generates a borrow; other- wise, C is unaffected.
Page 303 SUBK Subtract from Accumulator Short Immediate Syntax [ label ] SUBK constant Operands constant Execution (PC) + 1 (ACC) – 8-bit positive constant Affects C and OV: affected by OVM. Not affected by SXM. Encoding 8-Bit Constant Description The 8-bit immediate value is subtracted, right-justified, from the accumulator with the result replacing the accumulator contents.
Page 304 SUBS Subtract from Low Accumulator with Sign-Extension Supressed Syntax Direct: [ label ] SUBS Indirect: [ label ] SUBS {ind} [, next ARP ] Operands next ARP Execution (PC) + 1 (ACC) – (dma) Affects OV; affected by OVM. Affects C. Not affected by SXM.
Page 305 SUBT Subtract from Accumulator with Shift Specified by T Register Syntax Direct: [ label ] SUBT dma Indirect: [ label ] SUBT {ind} [, next ARP ] Operands dma 127 next ARP Execution (PC) + 1 T register (3 – 0) (ACC) - [(dma) (ACC) If SXM = 1:...
Page 306 Set External Flag Syntax [ label ] Operands None Execution (PC) + 1 external flag (XF) pin and status bit Affects XF. Encoding Description The XF pin and the XF status bit in status register ST1 are set to logic 1. XF may also be loaded by the LST1 and RXF instructions.
Page 307 TBLR Table Read Syntax Direct: [ label ] TBLR dma Indirect: [ label ] TBLR {ind} [, next ARP ]] Operands next ARP Execution (PC) + 1 (PFC) (ACC(15–0)) If (repeat counter) Then (pma, addressed by PFC) dma, Modify AR(ARP) and ARP as specified, (PFC) + 1 PFC, (repeat counter) –...
Page 308 TBLR Table Read Cycles Cycle Timings for a Single Instruction PI/DI PI/DE PE/DI PE/DE PR/DI PR/DE Table in on-chip RAM: 3 + d + p Table in on-chip ROM: 4 + d + p Table in external memory: 3+d+p 4+2p 4+d+2p 4+d+p Cycle Timings for a Repeat Execution...
Page 309 TBLW Table Write Syntax Direct: [ label ] TBLW dma Indirect: [ label ] TBLW {ind} [, next ARP ] Operands next ARP Execution (PC) + 1 (PFC) (ACC(15–0)) If (repeat counter) Then dma (pma, addressed by PFC), Modify AR(ARP) and ARP as specified, (PFC) + 1 PFC, (repeat counter) –...
Page 310 TBLW Table Write Cycles Cycle Timings for a Single Instruction PI/DI PI/DE PE/DI PE/DE PR/DI PR/DE Table in on-chip RAM: 4 + d + p Table in on-chip ROM: not applicable Table in external memory: 3 + d + p 3+2p 4+d+2p 4+d+p...
Page 311 TRAP Software Interrupt Syntax [ label ] TRAP Operands None Execution (PC) + 1 stack Not affected by INTM; does not affect INTM. Encoding Description The TRAP instruction is a software interrupt that transfers program control to program memory location 30 and pushes the program counter plus one onto the hardware stack.
Page 312 Exclusive-OR with Accumulator Syntax Direct: [ label ] Indirect: [ label ] {ind} [, next ARP ] Operands next ARP Execution (PC) + 1 (ACC(15–0)) XOR dma ACC(15–0) (ACC(31–16)) ACC(31–16) Not affected by SXM. Encoding Direct: Data Memory Address Indirect: See Section 4.1 Description The low half of the accumulator is exclusive-ORed with the contents of the ad-...
Page 313 XORK XOR Immediate with Accumulator with Shift Syntax [ label ] XORK constant [, shift ] Operands 16-bit constant shift 15 (defaults to 0) Execution (PC) + 2 shift (ACC(30–0)) XOR [constant ACC(30–0) (ACC(31)) ACC(31) Encoding Shift 16-Bit Constant Description The left-shifted 16-bit immediate constant is exclusive-ORed with the accumu- lator, leaving the result in the accumulator.
Page 314 Zero Accumulator Syntax [ label ] Operands None Execution (PC) + 1 Encoding Description The contents of the accumulator are replaced with zero. The ZAC instruction has been implemented as a special case of LACK. (ZAC assembles as LACK Words Cycles Cycle Timings for a Single Instruction PI/DI...
Page 315 ZALH Zero Low Accumulator and Load High Accumulator Syntax Direct: [ label ] ZALH dma Indirect: [ label ] ZALH [ {ind} [, next ARP ] Operands dma 127 next ARP Execution (PC) + 1 ACC(15–0) (dma) ACC(31–16) Encoding Direct: Data Memory Address Indirect: See Section 4.1...
Page 316 ZALR Zero Low Accumulator, Load High Accumulator with Rounding Syntax Direct: [ label ] ZALR dma Indirect: [ label ] ZALR {ind} [, next ARP ] Operands dma 127 next ARP Execution (PC) + 1 8000h ACC(15–0) (dma) ACC(31–16) Encoding Direct: Data Memory Address Indirect:...
Page 317 ZALS Zero Accumulator, Load Low Accumulator with Sign-Extension Suppressed Syntax Direct: [ label ] ZALS Indirect: [ label ] ZALS {ind} [ next ARP ] Operands dma 127 next ARP Execution (PC) + 1 ACC(31–16) (dma) ACC(15–0) Not affected by SXM. Encoding Direct: Data Memory Address...
Page 318: Software Applications
This chapter provides explanations of how to use the various TMS320C2x pro- cessor and instruction set features along with assembly language coding ex- amples. More information about specific applications can be found in the book, Digital Signal Processing Applications with the TMS320 Family (literature number SPRA012A).
Page 319 When reset is activated by applying a low level voltage to the RS (reset) input for at least three cycles, the TMS320C2x terminates execution and forces the program counter (PC) to zero. Program memory location 0 normally contains a B (branch) instruction to direct program execution to the system initialization routine.
Page 320 Processor Initialization Example 5–1.Processor Initialization (TMS320C25) .title ’PROCESSOR INITIALIZATION’ .def RESET,INT0,INT1,INT2 .def TINT,RINT,XINT,USER .ref ISR0,ISR1,ISR2 .ref TIME,RCV,XMT,PROC * PROCESSOR INITIALIZATION FOR THE TMS320C25. * RESET AND INTERRUPT VECTOR SPECIFICATION. * BRANCHES FOR EXTERNAL AND INTERNAL INTERRUPTS. .sect ”vectors” RESET B INIT ;...
Page 321 Processor Initialization ; ZERO THE ACCUMULATOR. LARK AR7,60h ; POINT TO BLOCK B2. RPTK SACL ; STORE ZERO IN ALL 32 LOCATIONS. LRLK AR7,200h ; POINT TO BLOCK B0. RPTK SACL ; ZERO ALL OF PAGES 4 AND 5. LRLK AR7,300h ;...
Page 322 Processor Initialization INTM * ST0: XXXXXXXXX CNF0 CNF1 ST1: REGISTER ADDRESS DATA 0000h XXXX XXXX XXXX XXXX 0001h XXXX XXXX XXXX XXXX 0002h 1111 1111 1111 1111 0003h XXXX XXXX XXXX XXXX 0004h 1111 1111 11XX XXXX GREG 0005h 1111 1111 0000 0000 RESERVED XINT RINT...
Page 323 Processor Initialization 5.1.1 TMS320C26 Download/Bootstrapping Modes The TMS320C26 boot program allows three types of download: Mode 1: parallel download from an I/O port Mode 2: serial download from an RS232 port Mode 3: external memory (EPROM) download. Note: In all three modes, The download begins at data block B0 (0200h) in internal space and con- tinues until the length specified by the download mode is reached.
Page 324: Bio-Xf Handshake
Processor Initialization the BIO pin low. When the BIO pin goes low, the C26 inputs the data from port address zero and stores it in the currently available memory location. The C26 then drives the XF pin high to indicate to the host that the data has been re- ceived.
Page 325: Sequence For 8-Bit Transfers
Processor Initialization Figure 5–2. Sequence for 8-Bit Transfers X X X X X X X X STATUS WORD X X X X X X X X INTERRUPT WORD X X X X X X X X PROGRAM LENGTH X X X X X X X X PROG WORD 1 LOW X X X X X X X X PROG WORD 1 HIGH...
Page 326: Building Length From Status And Program Length Words
Processor Initialization Configuration Word Definitions STATUS (1 BIO–XF transfer) This is the first word sent to the C26. The bit fields for this word are given below. Bits D0, D1, D2 are the MSBs of the program length. Bit D3 selects the reset/download mode: 0 = reset only (no download) 1 = start download of the program Bit D4 selects the transmission/memory format:...
Page 327 Processor Initialization PROGRAM WORD (1 or 2 BIO–XF transfers) The next LENGTH program words are then loaded into the internal RAM fol- lowed by external data RAM at 0800h. In the 8-bit mode, two words are trans- ferred for each complete program word. That is, 4K transfers will result in up to 2K program words received.
Page 328: Rs232 Connection To The Tms320C26
Processor Initialization 5.1.1.2 Mode 2: Serial Download From an RS232 Port (8 Data Bits, 2 Stop Bits, 1 Start Bit) If the BIO signal is found to be high 39+2d cycles after reset, a test is made to determine if external global memory (EPROM, mode 3) is present. If this fails, a serial download is performed.
Page 329 Logic high (1) = Transmission in progress or checksum valid Logic low (0) = Checksum error RS232 line levels are not TTL-compatible. RS232 line drivers and receivers, such as the Texas Instruments 75188 and 75189, must be used to interface to the RS232 level. Example 5–4. RS232 Transfer Protocol BIO high ;at reset signals either serial or EPROM load...
Page 330: Sequence For Rs232 Transfer (8 Data Bits Only)
Processor Initialization Figure 5–6. Sequence for RS232 Transfer (8 Data Bits Only) BAUD DETECT WORD STATUS WORD INTERRUPT WORD PROGRAM LENGTH PROG WORD 1 LOW PROG WORD 1 HIGH PROG WORD 2 LOW 2 Length Transfers PROG WORD 2 HIGH REPEAT CHECKSUM LOW CHECKSUM HIGH...
Page 331: Building Length From Status And Program Length Words
Processor Initialization INTERRUPT (1 RS232 transfer) The third word defines the interrupt and final memory configuration to be installed after bootstrapping. During the bootload process, blocks B0, B1 and B3 are configured as data and are always loaded first. This word is loaded into the C26 with a single transfer with the upper bits being masked off.
Page 332 Processor Initialization a precalculated checksum, and the C26 returns the status on the XF line and port PA0. The checksum status definitions are shown below. In the RS232 mode, the byte sequence is low to high. XF=0 or PA0= 00h, indicates a checksum error. XF=1 or PA0=0FFh, indicates a correct checksum.
Page 333: External Memory Byte Ordering
Processor Initialization It is impossible to download from an EPROM if the global memory select pin BR (bus request) is not used to enable the EPROM. The advantage of this method is that BR can also be ORed with MSC to generate a one-wait state ready condition for global memory access.
Page 334 Processor Initialization Example 5–5.TMS320C26BFNL Bootloader ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––; TMS320C26BFNL Bootloader 1/15/92 ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––; .text .title ”*** Texas Instruments TMS320C26 Bootloader ***” .mmregs *–––––––––––––––––––––––––––––––––––––––––––––––––– MEMORY: .set 060h ;Temporary Register LENGTH: .set 061h ;Program–Length CHECK: .set 062h ;Checksum MASKFF: .set 063h ;Low–Byte–Mask WORD8L: .set 064h ;Low–Byte Data Word WORD8H: .set 065h ;High–Byte Data Word...
Page 335 Processor Initialization READ FUNCTIONAL MODE 36+2d CYCLES AFTER RESET BIO = 0 –––> COPROCESSOR (PARALLEL I/O) LOAD BIO = 1 –––> MULTIPROCESSOR (SERIAL) MODE –OR– BYTE WIDE EPROM LOAD <–– NEW *–––––––––––––––––––––––––––––––––––––––––––––––––– bioz COPRO1 ;BIO low –> COPROCESSOR MULTI ;Zero indicates B –>PASS lark AR1, 0 ;if pass test NORMAL data space...
Page 336 Processor Initialization SACL LENGTH ;into Program–Length LRLK AR7,ADRESS ;Init. address AR6,LENGTH ;Init. counter value STATUS,POSST ;D4 (16 bit format)= high? LOW8L,*,AR7 ;No, then go to LOW8L LOW16 BIOZ LOW16 ;BIO–Input = high? ;Set Ready–Signal HIGH16 BIOZ READ16 ;BIO–Input = low? HIGH16 READ16 *,PA0...
Page 337 Processor Initialization PROG,*,AR0 ;branch to user prog (B0) ;––––––––––––––––––––––––––––– READ MODE READP ;MODE ? READS: ;MULTIPROCESSOR–>RS232 link LARK AR2,0 ;init. byte value WSTBIT BIOZ STOK,*,AR1 ;wait for start bit falling edge WSTBIT ;–––––––––––––––––––––––––––––––––––––––––––––––––; ; Note: The following sequence uses a shift and ;...
Page 338 Processor Initialization *********************************************************** EPROM BOOTLOAD *********************************************************** Full_Load: lrlk AR1, LEPROM Test_Load1: lark AR2, 080h ; Entry = Global DS AR2, GREG ; Load length = AR1 Test_Load2: lrlk AR7, EPROM–1 ; Entry = Norm DS lrlk AR3, ADRESS ; load destination moreEPROM: adrk ;...
Page 339 5.2.1 Subroutines The TMS320C2x has a 16-bit program counter (PC) and a eight-level hard- ware stack for PC storage. The CALL and CALA subroutine calls store the cur- rent contents of the program counter on the top of the stack. The RET (return from subroutine) instruction then pops the top of the stack to the program counter.
Page 340 ; RESTORE STATUS REGISTER ST0. The hardware stack is allocated for use in interrupts, subroutine calls, pipe- lined instructions, and debugging. The TMS320C2x disables all interrupts when it takes an interrupt trap. If interrupts are enabled more than one instruc- tion before the return of the interrupt service routine, the routine can also be interrupted, thus using another level of the hardware stack.
Page 341 Program Control 5.2.2 Software Stack Provisions have been made on the TMS320C2x for extending the hardware stack into data memory. This is useful for deep subroutine nesting or stack overflow protection. Use the PUSH and POP instructions to access the hardware stack via the ac- cumulator.
Page 342 5.2.3 Timer Operation The TMS320C2x 16-bit on-chip timer and its associated interrupt perform vari- ous functions at regular time intervals. On the TMS320C25, the timer is a down counter that is continuously clocked by CLKOUT1 and counts (PRD + 1) cycles of CLKOUT1.
Page 343 When programming time-critical high-computational tasks, it is often neces- sary to repeat the same operation many times. For these tasks, the TMS320C2x has repeat instructions that allow the execution of the next single instruction N+1 times. N is defined by an eight-bit repeat counter (RPTC), which is loaded by the RPT or RPTK instructions.
Page 344 Program Control Programs, such as those implementing digital filters, require loops that execute in a minimum amount of time. Example 5–9 shows the use of the RPT or RPTK instructions. Example 5–9.Instruction Repeating THIS ROUTINE USES THE RPT INSTRUCTION TO SET UP THE LOOP COUNTER IN ONE CYCLE. THE FOLLOWING EQUATION IS IMPLEMENTED IN THIS ROUTINE: –––––...
Page 345 Following a specific time or data processing path may then result in se- lecting one of several processing options. You can program a simple computed GOTO in the TMS320C2x by using the CALA instruction. This instruction uses the contents of the accumulator as the direct address of the call.
Page 346 On the TMS320C2x, the program counter is stored automatically on the hardware stack. If there is any important information in the other TMS320C2x registers, such as the status or auxiliary registers, these must be saved by software command. A stack in data memory, identified by an auxiliary register, is useful for storing the machine state when processing interrupts.
Page 347 Interrupt Service Routine Example 5–11. Context Save (TMS320C25) .title ’CONTEXT SAVE’ .def SAVE * CONTEXT SAVE ON SUBROUTINE CALL OR INTERRUPT. * ASSUME AR7 IS THE STACK POINTER AND AR7 = 128. SAVE LARP ;(ARP) ARB, 7 ARP, AR7 = 128 *–...
Page 348 Interrupt Service Routine Example 5–12. Context Restore (TMS320C25) .title ’CONTEXT RESTORE’ .def RESTOR * CONTEXT RESTORE AT THE END OF A SUBROUTINE OR INTERRUPT. * ASSUME AR7 IS THE STACK POINTER AND AR7 = 105. RESTOR LARP AR7 ; (ARP), ARB, 7 ARP, AR7 = 105...
Page 349 Interrupt Service Routine 5.3.2 Interrupt Priority Interrupts on the TMS320C2x are prioritized in hardware. This allows inter- rupts that occur simultaneously to be serviced in a prioritized order. Some- times priority may be determined by frequency or rate of occurrence. An infre- quent, but lengthy, ISR might need to be interrupted by a more frequently oc- curring interrupt.
Page 350: Memory Management
Memory Management 5.4 Memory Management The structure of the TMS320C2x memory map is programmable and can vary for each application. Instructions are provided for moving blocks of data or pro- gram memory, configuring a block of on-chip data RAM as program memory, and defining part of external data memory as global.
Page 351 Memory Management The TBLR instruction is another method for transferring data from program memory into data memory. When the TBLR instruction is used, a calculated, rather than predetermined, location of a block of data in program memory may be specified for transfer. A routine using this approach is shown in Example 5–16.
Page 352 TMS320C26 The reconfigurable memory space of the TMS320C26 is different in both the number of configurable blocks and the size of the blocks. For the TMS320C2x, only 256 words in Block B0 are reconfigurable using the CNFD and CNFP instructions. The TMS320C26 has three reconfigurable blocks —B0, B1 and B3—each 512 words in length.
Page 353: On-Chip Ram Configurations
Memory Management Figure 5–9. On-Chip RAM Configurations Program Data Memory Locations Data 0–5 Memory-Mapped Registers (0000h–0005h) Data 96–127 Block B2 (0060h–007Fh) Data 512–767 Block B0 (0200h–02FFh) Data 768–1023 Block B1 (0300h–03FFh) Memory Program Data Locations Data 0–5 Memory-Mapped Registers (0000h–0005h) Data 96–127 Block B2 (0060h–007Fh)
Page 354 Memory Management Example 5–20. Configuring and Using On-Chip RAM .title ’ADAPTIVE FILTER’ .def ADPFIR .def X, Y * THIS 128-TAP ADAPTIVE FIR FILTER USES ON-CHIP MEMORY BLOCK B0 FOR COEFFICIENTS * AND BLOCK B1 FOR DATA SAMPLES. THE NEWEST INPUT SHOULD BE IN MEMORY LOCATION X * WHEN CALLED.
Page 355 The code in Example 5–22 for the TMS320C26 is equivalent to the code in Example 5–21 written for the rest of the TMS320C2x. Software Applications...
Page 356 Memory Management Example 5–21. Program Execution from On-Chip Memory .title ”ON-CHIP RAM PROGRAM EXECUTION EXAMPLE” .width 96 .option X .text RESET B INIT * BRANCHES FOR EXTERNAL OR INTERNAL INTERRUPTS FOLLOW HERE AT THE DESIGNATED * LOCATIONS AS REQUIRED. .space (32–($–RESET))*16 * A BRANCH INSTRUCTION AT PROGRAM MEMORY LOCATION 0 DIRECTS PROCESSOR EXECUTION * HERE.
Page 357 Memory Management FILOUT,PA2 ; OUTPUT LAST FILTER OUTPUT. FILIN,PA2 ; INPUT NEW SIGNAL SAMPLE. LRLK AR1,SIGNAL ; POINT AR1 TO SIGNAL DATA TO PROCESS. ; CLEAR THE ACCUMULATOR. MPYK ; CLEAR THE P REGISTER. RPTK ; REPEAT MACD INSTRUCTION FOR 16 TAPS. MACD COEF,*–...
Page 358 Memory Management Example 5–22. Program Execution From On-Chip Memory (TMS320C26) .file onchip26 .title ON-CHIP RAM PROGRAM EXECUTION EXAMPLE FOR THE TMS320C26 .width 96 .option PGMBO .set 0FA00h BLKSIZ .set 00200h ; BLOCKSIZE OF TMS320C26 .text RESET B INIT,*,AR1 ARP = AR1 * BRANCHES FOR EXTERNAL OR INTERNAL INTERRUPTS FOLLOW HERE AT THE DESIGNATED * LOCATIONS AS REQUIRED.
Page 359 Memory Management COEF .label C1_START .word 385,-1196,1839,-2009 .word 1390,407,-4403,19958 .word 19958,-4403,407,1390 .word -2009,1839,-1196,385 COEFE .label C1_END COEFL .equ COEFE-COEF ; Coefficient data length * Data page 0 (Block B2) – Data memory labels. .bss DRR,1 ; Serial port data receive register .bss DXR,1 ;...
Page 360 Fundamental Logical and Arithmetic Operations 5.5 Fundamental Logical and Arithmetic Operations Although the TMS320C2x instruction set is oriented toward digital signal pro- cessing, the same fundamental operations of a general-purpose processor are included. This section explains basic operations of the TMS320C2x cen- tral arithmetic logic unit (CALU), particularly accumulator operations, the sta- tus register effect on data processing, and bit manipulation.
Page 361 Bit testing is useful in control applications where a number of states or condi- tions may be latched externally and read into the TMS320C2x via an IN instruction. At this point, individual bits can be tested and branches taken for appropriate processing.
Page 362 Fundamental Logical and Arithmetic Operations Example 5–23. Using BIT and BBZ * THIS ROUTINE USES THE BIT INSTRUCTION TO TEST THE CONDITION OF AN EXTERNAL MUX. * BIT 4 DETERMINES THE UTILITY OF THE REMAINING DATA. IF ZERO, A COUNTER IS * INCREMENTED.
Page 363 5.6.1 Overflow Management The TMS320C2x has four features that can be used to handle overflow man- agement: the branch on overflow conditions, accumulator saturation (overflow mode), product register right shift, and accumulator right shift. These features provide several options for overflow protection within an algorithm.
Page 364 Scaling and normalizing are implemented on the TMS320C2x via right and left shifts in the accumulator and shifts of data on the incoming path to the accumulator.
Page 365 Advanced Arithmetic Operations Second, for bit-reversed carry addition in the ARAU, the logic of the ARAU pro- pogates the carries from any half adder to the right , instead of left as in a nor- mal addition. In otherwords, bit-reversed carry addition works as if you were looking at the inputs and outputs with a mirror;...
Page 366 Advanced Arithmetic Operations Bit-reversed carry addition is effective as a logical shifter that does not use the accumulator in any way. Here are some other applications: Suppose you want to do a decimation in frequency FFT. In this case, the DFT block size decreases by one-half for every stage of the FFT.
Page 367 Advanced Arithmetic Operations Example 5–27. Using the AR0 Test Bit to Calculate the Square Root of a Long Integer *********************************************************** * LNG_SQRT.ASM Calculates the 16 bit sqrt of a long int * long lng_sqrt(long); /* C prototype */ |–––––––––––| This routine uses a succesive approximation technique that |–––––––––––| holds both the test bit and...
Page 368 Advanced Arithmetic Operations 5.6.4 Moving Data Many DSP applications must perform convolution operations or other opera- tions similar in form. These operations require data to be shifted or delayed. The DMOV, LTD, and MACD instructions can perform the needed data moves for convolution.
Page 369: Macd Operation
Advanced Arithmetic Operations Figure 5–10. MACD Operation Program Data Block B0 Block B1 0FF00h 300h 0FF01h 301h 0FF02h 302h (Coefficients) (Samples) Also, in Example 5–28, the summation in the above equation is performed in the reverse order, that is, from K = 2 to 0, because of the operation of the data move function.
Page 370 The TMS320C2x hardware multiplier normally performs 2s-complement 16-bit by 16-bit multiplies and produces a 32-bit result in one processor cycle. A single TMS320C2x instruction, MPYU, can be used to multiply two 16-bit un- signed numbers. To multiply two operands, one operand must be loaded into the T register (TR).
Page 371 Advanced Arithmetic Operations Example 5–30. Multiply-Accumulate Using the MAC Instruction (TMS320C25) CLOCK TOTAL CLOCK PROGRAM TOTAL PROGRAM CYCLES CYCLES MEMORY MEMORY LARP LRLK AR1,300h CNFP MPYK RPTK N–1 0FF00h,*+ ; 3 + N APAC 11 + N Example 5–31. Multiply-Accumulate Using the LTA-MPY Instruction Pair CLOCK TOTAL CLOCK PROGRAM...
Page 372: Execution Time Vs. Number Of Multiply-Accumulates (Tms320C25)
Advanced Arithmetic Operations Figure 5–11. Execution Time vs. Number of Multiply-Accumulates (TMS320C25) = MAC Implementation = LTA-MPY Implementation = Break-Even Point Number of Multiply-Accumulates to Be Performed 5-55...
Page 373: Program Memory Vs. Number Of Multiply-Accumulates
Number of Multiply-Accumulates to Be Performed In numerical analysis, it is often necessary to square numbers as well as add or subtract. The TMS320C2x has two instructions, SQRA and SQRS, that ac- complish this in a single machine cycle. The result of the previous operation in the PR is first added to the accumulator if SQRA is used, or subtracted from the accumulator if SQRS is used.
Page 374 MAC instruction by using the product shift mode on the TMS320C2x. This mode, controlled by two bits in the PM field of status register ST1, shifts the value from the PR while it is transferred to the accumulator. The contents of the PR are not shifted.
Page 375 Advanced Arithmetic Operations Integer and fractional division can be implemented with the SUBC instruction as shown in Example 5–34 and Example 5–35, respectively. When you imple- ment a divide algorithm, it is important to know if the quotient can be repre- sented as a fraction and the degree of accuracy to which the quotient is to be computed.
Page 376 Advanced Arithmetic Operations Example 5–34. Using SUBC for Integer Division THIS ROUTINE IMPLEMENTS INTEGER DIVISION. NUMERA ; GET SIGN OF QUOTIENT. DENOM SACH TEMSGN ; SAVE SIGN OF QUOTIENT. DENOM SACL DENOM ; MAKE DENOMINATOR POSITIVE. NUMERA ; ALIGN NUMERATOR. IF denominator AND numerator ARE ALIGNED, DIVISION CAN START HERE.
Page 377 Digital Signal Processing Applications with the TMS320 Family (literature number SPRA012A). Operations in the TMS320C2x central ALU are performed in 2s-complement fixed-point notation. To implement floating-point arithmetic, operands must be converted to fixed point for arithmetic operations, and then converted back to floating point.
Page 378 Advanced Arithmetic Operations Example 5–36. Using NORM for Floating-Point Multiply THIS SUBROUTINE PERFORMS A FLOATING-POINT MULTIPLY USING THE NORM INSTRUCTION. THE INPUTS AND OUTPUTS ARE OF THE FORM: C = MC * 2**EC SINCE THE MANTISSAS, MA AND MB, ARE NORMALIZED, MC CAN BE NORMALIZED WITH A LEFT SHIFT OF EITHER 0 OR 1 IN THE ACCUMULATOR.
Page 379 Numerical analysis, floating-point computations, or other operations may re- quire arithmetic to be executed with more than 32 bits of precision. Since the TMS320C2x processors are 16/32-bit fixed-point devices, software is required for the extended-precision of arithmetic operations. A subroutine that performs the extended-arithmetic function for the TMS320C25 is provided in the exam- ples of this section.
Page 380 Advanced Arithmetic Operations The TMS320C25 has two features that help to make extended-precision cal- culations more efficient. One of the features is the carry status bit. This bit is affected by all arithmetic operations of the accumulator (ABS, ADD, ADDC, ADDH, ADDK, ADDS, ADDT, ADLK, APAC, LTA, LTD, LTS, MAC, MACD, MPYA, MPYS, NEG, SBLK, SPAC, SQRA, SQRS, SUB, SUBB, SUBC, SUBH, SUBK, SUBS, and SUBT).
Page 381 Advanced Arithmetic Operations Example 5–39 shows an implementation of two 64-bit numbers added to each other to obtain a 64-bit result. This example adds 32-bit parts and generates a carry (C) bit in the accumulator. Example 5–39. 64-Bit Addition * TWO 64-BIT NUMBERS ARE ADDED TO EACH OTHER PRODUCING A 64-BIT RESULT. THE * NUMBERS (X3,X2,X1,X0) (Y3,Y2,Y1,Y0)
Page 382 Advanced Arithmetic Operations – – – – – – (SUBB) – (SUBB) – (SUBH) – – (SUBH) The coding in Example 5–40 shows the advantage of using the carry (C) sta- tus bit on the TMS320C25. Example 5–40. 64-Bit Subtraction * TWO 64-BIT NUMBERS ARE SUBTRACTED, PRODUCING A 64-BIT RESULT.
Page 383 Advanced Arithmetic Operations The second feature of the TMS320C25 that assists in extended-precision cal- culations is the MPYU (unsigned multiply) instruction. The MPYU instruction allows two unsigned 16-bit numbers to be multiplied and the 32-bit result to be placed in the product register in a single cycle. Efficiency is gained by generat- ing partial products from the 16-bit portions of a 32-bit or larger value instead of having to split the value into 15-bit or smaller parts.
Page 384 Advanced Arithmetic Operations ; ACC = X0*Y1 + X0*Y0*2**–16 MPYA ; T = X1, P = X1*Y1, ; ACC = X1*Y0 + X0*Y1 + X0*Y0*2**–16 SACL ; SAVE SACH ; SAVE PARTIAL ZALS ; P = X1*Y1, ; ACC = (X1*Y0 + X0*Y1)*2**–16 ;...
Page 385 The technique of companding allows the digital sample information corre- sponding to a 13-bit dynamic range to be transmitted as 8-bit data. For proces- sing in the TMS320C2x, it is necessary to convert the 8-bit (logarithmic) sign- magnitude data to a 16-bit 2s-complement (linear) format. Prior to output, the linear result must be converted to the compressed or companded format.
Page 386: Program Space And Time Requirements For Μ-/A-Law Companding
Application-Oriented Operations µ Table 5–1. Program Space and Time Requirements for -/A-Law Companding Time (µs) Required † Function Memory Words Program Cycles Initialization Loop ‡ Program Data TMS320C25 µ-Law: Compression Expansion A-Law: Compression Expansion † Assuming initialization ‡ Worst case In expanding from the 8-bit data to the 13-bit linear representation, table look- up is very effective because the table length is only 256 words.
Page 387 Application-Oriented Operations 5.7.2 FIR/IIR Filtering Digital filters are a common requirement for digital signal processing systems. The filters fall into two basic categories: finite impulse response (FIR) and Infi- nite impulse response (IIR) filters. For either category of filter, the coefficients of the filter (weighting factors) may be fixed or adapted during the course of the signal processing.
Page 388 IIR filter with equivalent sharpness at the cutoff frequencies and distortion and attenuation in the pass- bands and stopbands. The TMS320C2x can help solve this problem by mak- ing longer filters feasible to implement. This is accomplished by allowing the coefficients to be fetched from program memory at the same time as a sample is being fetched from data memory.
Page 389 Application-Oriented Operations LRLK AR2,COEFFD ; LOAD ADDRESS OF COEFFICIENTS. LRLK AR3,LASTAP ; LOAD ADDRESS OF DATA SAMPLES. LARP ERRF ; errf = 2*B*e(i) ZALH *,AR3 ; ACC = bk(i)*2**16 ONE,15 ; ACC = bk(i)*2**16 + 2**15 *–,AR2 APAC ; ACC = bk(i)*2**16 + errf*x(i – k) + 2**15 SACH ;...
Page 390 Application-Oriented Operations Example 5–43. 256-Tap Adaptive FIR Filter .title ’ADAPTIVE FILTER’ .def ADPFIR .def X,Y THIS 256-TAP ADAPTIVE FIR FILTER USES ON-CHIP MEMORY BLOCK B0 FOR COEFFICIENTS AND BLOCK B1 FOR DATA SAMPLES. THE NEWEST INPUT SHOULD BE IN MEMORY LOCATION X WHEN CALLED.
Page 391 Application-Oriented Operations Example 5–44. Adaptive Filter Routine Concluded ADAPT ZALR *,AR3 ; LOAD ACCH WITH b255(i) & ROUND. MPYA *–,AR2 ; b255(i + 1) = b255(i) + P ; P = 2*beta*err(i)*x(i–254) SACH *+ ; STORE b255(i + 1). ZALR *,AR3 ;...
Page 392 Application-Oriented Operations 5.7.4 Fast Fourier Transforms (FFT) Fourier transforms are an important tool used often in digital signal processing systems. The purpose of the transform is to convert information from the time domain to the frequency domain. The inverse Fourier transform converts in- formation back to the time domain from the frequency domain.
Page 393: An In-Place Dit Fft With In-Order Outputs And Bit-Reversed Inputs
Application-Oriented Operations Figure 5–13. An In-Place DIT FFT With In-Order Outputs and Bit-Reversed Inputs Stage 1 Stage 2 Stage 3 x(0) x(0) x(1) x(4) x(2) x(2) x(3) x(6) x(4) x(1) x(5) x(5) x(6) x(3) x(7) x(7) LEGEND FOR TWIDDLE FACTOR: W 0 = W 1 = W 2 =...
Page 394: Bit-Reversal Algorithm For An 8-Point Radix-2 Dit Fft
Application-Oriented Operations Table 5–3. Bit-Reversal Algorithm for an 8-Point Radix-2 DIT FFT Index Bit Pattern Bit-reversed Pattern Bit-reversed Index An addressing feature that uses reverse carry-bit propagation allows the TMS320C25 to scramble the inputs or outputs while it is performing the I/O. The addressing mode is part of the indirect addressing implemented with the auxiliary registers and the associated arithmetic unit.
Page 395 Application-Oriented Operations The following list shows the contents of auxiliary register AR1 when AR0 is ini- tialized with a value of 8 (8-point FFT) and when data is being transferred by the code that follows. AR0: 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0...
Page 396 Application-Oriented Operations Example 5–45. FFT Macros COMBO $MACRO R1,I1,R2,I2,R3,I3,R4,I4 CALCULATE PARTIAL TERMS FOR R3, R4, I3, AND I4. :R3:,14 ; ACC : = (1/4) (R3) :R4:,14 ; ACC : = (1/4) (R3 + R4) SACH :R3:,1 ; R3 : = (1/2) (R3 + R4) :R4:,15 ;...
Page 397 Application-Oriented Operations Example 5–45. FFT Macros (Continued) SACH :QI:,1 ; QI : = (1/2) (QI – QR) :QR:,15 ; ACC : = (1/4) (QI + QR) SACH :QR:,1 ; QR : = (1/2) (QI + QR) :PR:,14 ; ACC : = (1/4) (PR) :QR: ;...
Page 398: Fft Memory Space And Time Requirements
Application-Oriented Operations Example 5–46. An 8-Point DIT FFT .set 00 .set 01 .set 02 .set 03 .set 04 .set 05 .set 06 .set 07 .set 08 .set 09 .set 10 .set 11 .set 12 .set 13 .set 14 .set 15 .set 16 WVALUE .set 5A82h ;...
Page 399 Digital control algorithms deal with the processing of digital signals and are similar to DSP algorithms. The TMS320C2x instruction set can there- fore be used very effectively in digital control systems.
Page 400 Application-Oriented Operations Example 5–47. PID Control .title ’PID CONTROL’ .def PID THIS ROUTINE IMPLEMENTS A PID ALGORITHM. UN .set ; OUTPUT OF CONTROLLER E0 .set ; LATEST ERROR SAMPLE E1 .set ; PREVIOUS ERROR SAMPLE E2 .set ; OLDEST ERROR SAMPLE K1 .set ;...
Page 401 Software Applications 5-84...
Page 402 Chapter 6 Hardware Applications The TMS320C2x has the power and flexibility to satisfy a wide range of system requirements. The 128K-word address space for program and data memory can be used to interface external memories or to implement single-chip solu- tions.
Page 403 Powerup Reset Circuit The reset circuit shown in Figure 6–1 performs a powerup reset, that is, the TMS320C2x is reset when power is applied. Note that the switch circuit must include debounce circuitry. Driving the RS signal low initializes the processor.
Page 404: Powerup Reset Circuit
System Control Circuitry Figure 6–1. Powerup Reset Circuit TMS320C25 +5 V R 1 = 1 MΩ C 1 = 0.47 µF DGND For proper system initialization, the reset signal must be applied for at least three CLKOUT cycles, that is, 300 ns for a TMS320C25 operating at 40 MHz. Upon powerup, it can take from several to hundreds of milliseconds before the system oscillator reaches a stable operating state.
Page 405: Voltage On Tms320C25 Reset Pin
System Control Circuitry Figure 6–2. Voltage on TMS320C25 Reset Pin Voltage τ V = V CC (1 – e – t / V CC t 0 = 0 t 1 Time The duration of the low pulse on the reset pin is approximately t , which is the time it takes for the capacitor C to be charged to 1.5 V.
Page 406: Crystal Oscillator Circuit
System Control Circuitry 6.1.2 Crystal Oscillator Circuit The crystal oscillator circuit shown in Figure 6–3 is designed to operate at 40.96 MHz. Since crystals with fundamental oscillation frequencies of 30 MHz and above are not readily available, a parallel-resonant third-overtone oscilla- tor is used.
Page 407: Magnitude Of Impedance Of Oscillator Lc Network
System Control Circuitry At frequencies significantly lower than ω , the 1/(ωC) term in (3) becomes the dominating term, while ωL can be neglected. This gives In (5), the LC circuit appears inductive at frequencies lower than ω . On the other hand, at frequencies much higher than ω...
Page 408 READY, RS, BIO, and HOLD, and the propagation delay of HOLDA (hold ac- knowledge). The additional loading on outputs induced by the XDS is compre- hended in the XDS and TMS320C2x device design, thus allowing the user the full drive as specified in the TMS320C2x device data sheet. The DC loading characteristics of inputs is defined in Chapter 9 of the XDS/22 TMS320C2x Emulator User’s Guide (literature number SPDU055).
Page 409 System Control Circuitry The target system should drive the data bus only when the following conditions are met: HOLDA is active, or DS, PS, or IS is active and R/W is high. The XDS hardware uses the data bus only while the above signals are inactive. When these rules are not followed, the XDS gives a PROCESSOR SYNC LOST 1160 error.
Page 410 System Control Circuitry The dynamic RAM substitution memory always uses more than one clock to return data. An access to address space mapped to the dynamic substitution memory is accompanied by the assertion of DS or PS, and STRB. When the target logic generates a READY high condition, the device appears to com- plete the memory cycle by driving DS, PS, IS, or STRB to their inactive states at their normal switching times.
Page 411 System Control Circuitry Stack Usage. An interrupt is used to halt the device being emulated, thereby using one of the emulated device stack locations. When an XDS is to be used, the applications programmer should reserve one level of the stack for code de- velopment.
Page 412: Iack
(see subsection 6.2.3). With no wait states, the READY input to the TMS320C2x can be pulled high. If one or more wait states are re- quired, the READY input must be driven low during the cycles in which the TMS320C2x enters a wait state.
Page 413 Program memory in a TMS320C2x system can be implemented through the use of PROMs. Two different approaches for interfacing PROMs to the TMS320C2x can be taken, depending on whether or not any of the memories in the system require wait states. When no wait states are required for any of the memories, READY can be tied high, and the interface to the PROMs be- comes a direct connection.
Page 414 Interfacing Memories meets the TMS320C2x timing requirements must be provided. An efficient method of accomplishing this is to use one section of circuitry to generate the address decode, and a second, independent section to generate the READY signal. These two approaches are discussed in this section. For more detailed information, see Hardware Interfacing to the TMS320C25 (literature number SPRA014A).
Page 415: Direct Interface Of Tbp38L165-35 To Tms320C25
Interfacing Memories Figure 6–5. Direct Interface of TBP38L165-35 to TMS320C25 TBP38L165-35 74ALS04 STRB +5 V 1k Ω READY TBP38L165-35 Hardware Applications 6-14...
Page 416: Interface Timing Of Tbp38L165-35 To Tms320C25
Interfacing Memories Figure 6–6. Interface Timing of TBP38L165-35 to TMS320C25 CLKOUT1 t a(SL) STRB t su(A) Valid A15–A0, t dis t a(A) D15–D0 Data In The most critical timing parameters of the TBP38L165 -35 direct interface to the TMS320C25 are summarized in Table 6–1. Table 6–1.
Page 417 Interfacing Memories Address decoding is implemented by the 74AS138. This decoding separates the program space into eight segments of 8K words each. The first four of these segments (lower 32K of address space) are enabled by the Y0, Y1, Y2, and Y3 outputs of the 74AS138.
Page 418: Interface Of Tbp38L165-35 To Tms320C25
Interfacing Memories Figure 6–7. Interface of TBP38L165-35 to TMS320C25 TMS320C25 TBP38L165-35 74AS138 MEMSEL 1 kΩ +5 V +5 V 74AS20 1 kΩ 74AS30 READY STRB MEMSTRB 74AS04 TBP38L165-35 6-17...
Page 419: Interface Timing Of Tbp38L165-35 To Tms320C25 (Address Decoding)
Interfacing Memories Figure 6–8. Interface Timing of TBP38L165-35 to TMS320C25 (Address Decoding) CLKOUT1 CLKOUT2 t a(SL) STRB t su(A) MEMSTRB t a(S) PS, DS, IS, Valid A15–A0 MEMSEL READY t dis D15–D0 Data In The most critical timing parameters of the TBP38L165-35 interface with ad- dress decoding to the TMS320C25 are summarized in Table 6–2.
Page 420: Timing Parameters Of Tbp38L165-35 To Tms320C25 (Address Decoding)
6.2.2 Wait-State Generator The READY input of the TMS320C2x allows it to interface with memory and peripherals that cannot be accessed in a single cycle. The number of cycles in a memory or I/O access is determined by the state of the READY input. If READY is high when the TMS320C2x samples the READY input, the memory access ends at the next falling edge of CLKOUT1.
Page 421: One Wait-State Memory Access Timing
Interfacing Memories Figure 6–9. One Wait-State Memory Access Timing CLKOUT1 STRB A15–A0, Valid PS, DS, or IS Valid Ready D15–D0 (For Read Data In Operation) D15–D0 Data Out (For Write Operation) The information on the number of wait states required for a memory or periph- eral access is summarized in Table 6–3.
Page 422: Wait-State Generator Design
Interfacing Memories READY must remain high until it is sampled again, shortly after CLKOUT1 goes high. In Figure 6–10, READY remains high well after CLKOUT1 goes high. On the falling edge of CLKOUT2, J = 1 and K = Q = 1 are the inputs to the J-K flip-flop;...
Page 423: Wait-State Generator Timing
EPROMs can be a valuable tool for debugging TMS320C2x algorithms during the prototyping stages of a design, and may even be desirable for production. Two different EPROM interfaces to the TMS320C2x are discussed: a direct in- terface of an EPROM that requires no wait states, and EPROM interfaces that require one and two wait states.
Page 424: Interface Of Ws57C65F-12 To Tms320C25
Interfacing Memories Figure 6–12. Interface of WS57C65F-12 to TMS320C25 WS57C64F-12 TMS320C25 +5 V 1 kΩ PGM 27 74AS138 MEMSEL 74AS32 DTSTR STRB Wait-State Generator (One Wait State) 74AS30 +5 V 1 kΩ READY WS57C64F-12 6-23...
Page 425: Interface Timing Of Ws57C65F-12 To Tms320C25
Interfacing Memories Figure 6–13. Interface Timing of WS57C65F-12 to TMS320C25 CLKOUT1 CLKOUT2 STRB DTSTR PS, R/W, Valid A15–A0 MEMSEL READY D15–D0 Valid Table 6–4 summarizes the most critical timing parameters of the WS57C64F-12 interface to the TMS320C25. Table 6–4. Timing Parameters of WS57C64F-12 Interface to TMS320C25 Description Symbol Used in Value...
Page 426: Interface Of Tms27C64-20 To Tms320C25
Interfacing Memories Figure 6–14. Interface of TMS27C64-20 to TMS320C25 74ALS244A TMS27C64-20 TMS320C25 +5 V 1 kΩ PGM 27 74AS138 MEMSEL 74AS32 DTSTR STRB Wait-State Generator (Two Wait States) +5 V 74AS30 74ALS244A 1 kΩ READY TMS27C64-20 6-25...
Page 427: Interface Timing Of Tms27C64-20 To Tms320C25
Interfacing external RAM to the TMS320C2x can be useful for expanding inter- nal data memory or implementing additional RAM program memory. Static RAM can be used as data memory to extend the TMS320C2x 544-word inter- nal RAM. When used as program memory, object code can be downloaded into the RAM and executed.
Page 428: Timing Parameters Of Cy7C169-25 Interface To Tms320C25
Interfacing Memories In cases where RAMs of different speeds are used, separate schemes for ad- dress decoding and READY generation can be used to meet READY timing requirements in a manner similar to that used for the PROM interface de- scribed in subsection 6.2.1.
Page 429: Interface Of Cy7C169-25 To Tms320C25
Interfacing Memories Figure 6–16. Interface of CY7C169-25 to TMS320C25 CY7C169-25 TMS320C25 I/O 1 I/O 2 I/O3 READY I/O 4 74AS30 I/O 1 74AS32 I/O 2 74AS138 I/O 3 I/O 4 +5 V I/O 1 1 kΩ I/O 2 STRB I/O 3 I/O 4 I/O 1 MEMSEL...
Page 430: Interface Timing Of Cy7C169-25 To Tms320C25
Interfacing Memories Figure 6–17. Interface Timing of CY7C169-25 to TMS320C25 CLKOUT1 Valid A15–A0 READY STRB MEMSEL Read Cycle TMS320C25 D15–D0 CY7C169-25 D15–D0 MEMSEL Write Cycle TMS320C25 D15–D0 CY7C169-25 I/O 4 –I/O 1 6.2.5 Interface Timing Analysis When interpreting TMS320C25 timing specifications, particularly in the area of memory interface timing, it is necessary to understand clock input and clock timing relationships shown in timing diagrams as compared with the actual data sheet specifications.
Page 431 Interfacing Memories Clock input and internal clock timing relationships must be considered in the interpretation of output timing characteristics and requirements. At the clock input to the device, only the rising edges of the clock are used to initiate transi- tions on internal clocks and output signals.
Page 432 Interfacing Memories late t , consistency results in all of these related timings. If an interface is a(A) designed where t is met but t is not met because of actual signal su(D)R a(A) skews, the interface is still guaranteed to function with the TMS320C25. The same is true (but is not as likely) if an interface is designed where t is met a(A)
Page 433 HOLDA. This signal may be tied to the master TMS320C2x’s BIO pin. The slave’s XF pin may be used to indicate to the master when it has finished performing its task and needs to be repro- grammed or requires additional data to continue processing.
Page 434: Direct Memory Access Using A Master-Slave Configuration
In another application ex- ample, the TMS320C2x can serve as a dedicated graphics engine. Programs can be stored in TMS320C2x program ROM or downloaded via the system bus into program RAM. Data can come from PC disk storage or provided directly by the master CPU.
Page 435: Direct Memory Access In A Pc Environment
Direct Memory Access (DMA) Figure 6–19. Direct Memory Access in a PC Environment Master Address Local Address Program/Data Address Memory Data (RAM) Address Data Disk Controller Decode/ Address HOLD Arbitration Address Logic Data Ready HOLDA Address Local Program/Data Data Memory (RAM) Hardware Applications 6-34...
Page 436 For multiprocessing applications, the external memory of the TMS320C2x can be divided into local and global sections. Special registers and pins included on the TMS320C2x allow multiple processors to share up to 32K words of glob- al data memory space. This implementation facilitates efficient shared data multiprocessing in which data is transferred between two or more processors.
Page 437: Global Memory Communication
Global Memory Figure 6–20. Global Memory Communication TMS320C2x TMS320C2x Arbitration Logic READY READY A15–A0 A15–A0 Global Data Memory D15–D0 D15–D0 SYNC SYNC Sync Program Program Generation Clock Memory Memory Logic Hardware Applications 6-36...
Page 438: Clkr
PCM-coded digital representation of analog input samples. This PCM code is easily translated into linear form by the TMS320C2x for use in processing. The design discussed here and shown in Figure 6–21 uses a Texas Instruments TCM29C16 codec, interfaced through using the serial port of the TMS320C25.
Page 439: Interface Of Tms320C25 To Tcm29C16 Codec
Interfacing Peripherals Data on DX and DR are clocked by CLKX and CLKR, respectively. These clocks are required only during serial transfers on the TMS320C25. Note that the TMS320C25 is double-buffered. Figure 6–21. Interface of TMS320C25 to TCM29C16 Codec +5 V 500 kΩ...
Page 440 Interfacing Peripherals The format (FO) bit of status register ST1 is used to select the format (8-bit byte or 16-bit word) of the data to be received or transmitted. For interfacing the TMS320C25 to a codec, the format bit should be set to 1, formatting the data in 8-bit bytes.
Page 441 Refer to the TLC32040 data sheet for detailed information on timing and device functions. The AIC is easily interfaced to the TMS320C2x serial ports, as shown in Figure 6–22. The TMS320C2x can communicate with the AIC either synchro- nously or asynchronously, depending on the information in the control register.
Page 442: Interface Of Tlc32040 To Tms320C2X
FSR do not occur at the same time (see Figure 6–24). For proper opera- tion, the TXM bit in the TMS320C2x control register should be set to 0 so that the FSX pin of the TMS320C2x is configured as an input, the format (FO) sta- tus bit is set to 0, and the AIC WORD/BYTE pin is at logic high.
Page 443: Asynchronous Timing Of Tlc32040 To Tms320C2X
Digital-to-Analog (D/A) Interface The high-speed operation of the internal logic circuitry of the TLC7524 8-bit digital-to-analog (D/A) converter allows an interface to the TMS320C2x with a minimum of external circuitry. Figure 6–25 shows the interface circuitry, which consists of one SN74ALS138 3-to-8-line decoder used to decode the address of the peripheral.
Page 444: Interface Timing Of Tlc7524 To Tms320C2X
The TMS320C2x can be interfaced to 8-bit A/D converters, such as the TLC0820. However, because the control circuitry of the TLC0820 operates much more slowly than the TMS320C2x, it cannot be directly interfaced. In the TLC0820 to TMS320C2x interface design shown in Figure 6–27, the following...
Page 445: Interface Of Tlc0820 To Tms320C2X
Interfacing Peripherals Figure 6–27. Interface of TLC0820 to TMS320C2x Address Bus / 16 A15–A0 74ALS138 TLC0820 Mode +5 V +5 V To TMS320C2x STRB CLKOUT1 READY D15–D0 Data Bus / 16 The 74LS138 decodes the addresses assigned to the TLC0820. One of the addresses is used for a write operation;...
Page 446: Interface Timing Of Tlc0820 To Tms320C2X
Interfacing Peripherals With the TMS320C2x running at 20 MHz and the TLC0820 configured as slow memory, three wait states are necessary to provide a write pulse of sufficient length. After conversion has begun (with the rising edge of the WR signal), the TMS320C2x must wait at least 600 ns before the conversion result can be read.
Page 447: I/O Port Addressing
6.5.5 I/O Ports I/O design on the TMS320C2x is treated the same way as memory. The I/O address space is distinguished from the local program/data memory space by the IS signal. IS goes low at the beginning of the memory cycle. All other con- trol signals and timing parameters are the same as those for the program/data external memory interface.
Page 448: I/O Port Processor-To-Processor Communication
TMS320C2x I/O-port multiprocessing scheme, as shown in Figure 6–30. The TMS70C42 may be mapped into the TMS320C2x I/O space by using latches to store the transferred data. In a single or multiple I/O-port multiprocessing configuration, the four LSBs of the address bus are decoded to determine which of the 16 I/O ports on the TMS320C2x is being accessed.
Page 449: Echo Canceler
System Applications 6.6 System Applications The TMS320C2x is used in a wide variety of systems. Several applications in the areas of telecommunications, graphics and image processing, high-speed control, instrumentation, and numeric processing are described in the follow- ing paragraphs to illustrate basic approaches to system design with the TMS320C2x.
Page 450: High-Speed Modem
(that is, with no external devices). Figure 6–33 shows a voice coding sys- tem consisting of a TMS320C2x DSP, TCM29C16 codec or TLC32040 AIC, and optional external memory.
Page 451: Graphics System
In- dexed indirect addressing modes on the TMS320C2x allow matrices to be pro- cessed row by row when matrix multiplication is performed for 3-D image rota- tion, translation, and scaling.
Page 452: Robot Axis Controller Subsystem
TMS320C2x provides a host interface whereby a robot can communicate to a central host processor (see Figure 6–35). The TMS320C2x is also used in the closed-loop systems of disk drives for signal conditioning, filtering, high- speed computing, and multichannel multiplexing.
Page 453 Hardware Applications 6-52...
Page 454 Appendix A TMS320C25 and TMS320E25 Digital Signal Processors This appendix contains data sheet information on the TMS320C25 digital sig- nal processors family, which includes the following devices: TMS320C25 TMS320C25-33 TMS320C25-50 TMS320E25 Refer to Appendix B for data sheet information on the TMS320C26, to Appen- dix C for the TMS320C28, and to Appendix D for the military versions.
Page 455 TMS320C25 and TMS320E25 Digital Signal Processors TMS320C25 and TMS320E25 Digital Signal Processors...
Page 456 Appendix B TMS320C26 Digital Signal Processor This appendix contains data sheet information on the TMS320C26 digital sig- nal processor.
Page 457 TMS320C26 Digital Signal Processor TMS320C26 Digital Signal Processor...
Page 458 Appendix C TMS320C28 Digital Signal Processor This appendix contains data sheet information on the TMS320C28 digital sig- nal processor.
Page 459 TMS320C28 Digital Signal Processor TMS320C28 Digital Signal Processor...
Page 460 Instructions are first listed in a table according to cycle classification. Then each class of instructions is listed in another table, showing the number of cycles required for a TMS320C2x instruction to execute in a given memory configuration singly or in repeat mode. The column headings in the tables indi-...
Page 461: Tms320C2X Instructions By Cycle Class
TMS320C2x Instruction Cycle Timings D.1 TMS320C2x Instruction Cycle Timings Table D–1 lists the TMS320C2x instructions according to cycle classification. Table D–2 and Table D–3 show the number of cycles required for a given TMS320C2x instruction to execute in a given memory configuration when executed as a single instruction or in the repeat mode, respectively.
Page 462: Cycle Timings For Cycle Classes When Not In Repeat Mode
TMS320C2x Instruction Cycle Timings Table D–2. Cycle Timings for Cycle Classes When Not in Repeat Mode CLASS PI/DI PI/DE PE/DI PE/DE PR/DI PR/DE 2+d+p 2+d+p 2+d+p 2+2p 2+2p Table in on-chip RAM: 4+2p 5+d+2p Table in on-chip ROM: 4+2p 5+d+2p...
Page 463 TMS320C2x Instruction Cycle Timings Table D–2. Cycle Timings for Cycle Classes When Not in Repeat Mode (Concluded) CLASS PI/DI PI/DE PE/DI PE/DE PR/DI PR/DE XIII Source data in on-chip RAM: 3+2p 3+d+2p Source data in external memory: 4+2d 4+d+2p 4+2d+2p...
Page 464: Cycle Timings For Cycle Classes When In Repeat Mode
TMS320C2x Instruction Cycle Timings Table D–3. Cycle Timings for Cycle Classes When in Repeat Mode CLASS PI/DI PI/DE PE/DI PE/DE PR/DI PR/DE 1+n+nd 1+n+nd+p 1+n+nd 2n+nd 2n+nd+p 2n+nd n+nd 1+n+nd+p n+nd not repeatable Table in on-chip RAM: 2+2n+nd 3+n+2p 3+2n+nd+2p...
Page 465 Instruction Cycle Timings...
Page 466 Appendix E SMJ320C2x Digital Signal Processors This appendix contains data sheet information on the SMJ320C2x digital sig- nal processors family.
Page 467 SMJ320C2x Digital Signal Processors SMJ320C2x Digital Signal Processors...
Page 468 PRODUCTION DATA information is current as of publication date. Copyright 1992, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Page 469 Running Title—Attribute Reference 100-ns Instruction Cycle Time 1568 Words of Configurable On-Chip Data/Program RAM 256 Words of On-Chip Program ROM 128K Words of Data/Program Space Pin-for-Pin Compatible with the SMJ320C25 16 Input and 16 Output Channels 16-Bit Parallel Interface Directly Accessible External Data Memory Space Global Data Memory Interface 16-Bit Instruction and Data Words...
Page 470 Running Title—Attribute Reference description The SMJ320C26 Digital Signal Processor is a member of the TMS320 family of VLSI digital signal processors and peripherals. The TMS320 family sup- ports a wide range of digital signal processing applications, such as telecom- munications, modems, image processing, speech processing, spectrum anal- ysis, audio processing, digital filtering, high-speed control, graphics, and other computation intensive applications.
Page 471: Clkx
Running Title—Attribute Reference K2/28 L9/41 D2/15 B6/2 J11/46 V CC L6/35 L3/29 K9/42 D1/14 J1/24 MP/MC A6/1 V SS B1/10 K3/30 L10/43 C2/13 K10/45 C10/59 V SS K11/44 L4/31 B7/68 C1/12 E11/54 J10/47 V SS L2/27 K4/32 G11/50 B2/11 J2/25 READY B8/66 D11/56...
Page 472: Pin Nomenclature (Tms320E25
Running Title—Attribute Reference PIN NOMENCLATURE I/O/Z † NAME DEFINITION V CC 5-V supply pins. V SS Ground pins. Output from internal oscillator for crystal. X2/CLKIN Input to internal oscillator from crystal or external clock. CLKOUT1 Master clock output (crystal or CLKIN frequency/4). CLKOUT2 A second clock output signal.
Page 473 Running Title—Attribute Reference functional block diagram Appendix Title—Attribute Reference...
Page 474 Running Title—Attribute Reference PROGRAM BUS QIR(16) IR(16) ST0(16) ST1(16) RPTC(8) STRB PFC(16) IFR(6) READY CLKR HOLD HOLDA MCS(16) PC(16) CLKX STACK IACK RSR(16) ADDRESS (8 - 16) XSR(16) MP/MC PROGRAM DRR(16) INT(2-0) DXR(16) (256 x 16) TIM(16) INSTRUCTION PRD(16) A15–A0 IMR(6) GREG(8) D15–D0...
Page 475 Running Title—Attribute Reference architecture The SMJ320C26 architecture is based on the SMJ320C25 with a different in- ternal RAM and ROM configuration. The SMJ320C26 integrates 256 words of on-chip ROM and 1568 words of on-chip RAM compared to 4K words of on- chip ROM and 544 words of on-chip RAM for the SMJ320C25.
Page 476 Running Title—Attribute Reference The 32-bit accumulator is split into two 16-bit segments for storage in data memory. Additional shifters at the output of the accumulator perform shifts while the data is being transferred to the data bus for storage. The contents of the accumulator remain unchanged.
Page 477 Running Title—Attribute Reference (block B2) are always data memory, and all other blocks are programmable as either data or program memory. A data memory size of 1568 words allows the SMJ320C26 to handle a data array of 1536 words, while still leaving 32 loca- tions for intermediate storage.
Page 478 Running Title—Attribute Reference MEMORY MAPS AFTER A RESET OR CONF 0 1 MP/MC = 1 PROGRAM DATA 0 (0000h) 0 (0000h) INTERRUPTS ON-CHIP EXTER AND RESERVED MMRs (EXTERNAL) 5 (0005h) 31 (001Fh) 6 (0006h) 32 (0020h) RESERVED PAGE 0 95 (005Fh) 96 (0060h) ON-CHIP BLOCK B2...
Page 479 Running Title—Attribute Reference Figure 1A. Memory Maps Appendix Title—Attribute Reference E-14...
Page 480 Running Title—Attribute Reference MEMORY MAPS AFTER CONF 1 1 MP/MC = 1 PROGRAM DATA 0 (0000h) 0 (0000h) ON-CHIP INTERRUPTS EXTER MMRs AND RESERVED 5 (0005h) (EXTERNAL) 6 (0006h) 31 (001Fh) RESERVED 32 (0020h) PAGE 0 95 (005Fh) 96 (0060h) ON-CHIP BLOCK B2 127 (007Fh)
Page 481 Running Title—Attribute Reference Figure 1B. Memory Maps Appendix Title—Attribute Reference E-16...
Page 482 Running Title—Attribute Reference MEMORY MAPS AFTER CONF 2 1 MP/MC = 1 PROGRAM DATA 0 (0000h) 0 (0000h) ON-CHIP INTERRUPTS EXTERNAL MMRs AND RESERVED 5 (0005h) (EXTERNAL) 6 (0006h) 31 (001Fh) RESERVED PAGE 0 32 (0020h) 95 (005Fh) 96 (0060h) ON-CHIP BLOCK B2 127 (007Fh)
Page 483 Running Title—Attribute Reference Figure 1C. Memory Maps Appendix Title—Attribute Reference E-18...
Page 484 Running Title—Attribute Reference MEMORY MAPS AFTER CONF 3 1 MP/MC = 1 PROGRAM DATA 0 (0000h) 0 (0000h) ON-CHIP INTERRUPTS EXTERNAL MMRs AND RESERVED 5 (0005h) (EXTERNAL) 6 (0006h) 31 (001Fh) RESERVED PAGE 0 32 (0020h) 95 (005Fh) 96 (0060h) ON-CHIP BLOCK B2 127 (007Fh)
Page 485 Running Title—Attribute Reference Figure 1D. Memory Maps Appendix Title—Attribute Reference E-20...
Page 486 Running Title—Attribute Reference interrupts and subroutines The SMJ320C26 has three external maskable user interrupts INT2–INT0, available for external devices that interrupt the processor. Internal interrupts are generated by the serial port (RINT and XINT), by the timer (TINT), and by the software interrupt (TRAP) instruction.
Page 487 Running Title—Attribute Reference multiprocessing The flexibility of the SMJ320C26 allows configurations to satisfy a wide range of system requirements. The SMJ320C26 can be used as follows: A standalone processor. A multiprocessor with devices in parallel. A multiprocessor with global memory space. A peripheral processor interfaced via processor controlled signals to another device.
Page 488 Running Title—Attribute Reference in the direct addressing mode with a total of 512 pages, each page containing 128 words. E-23...
Page 489 Running Title—Attribute Reference Eight auxiliary registers (AR0–AR7) provide flexible and powerful indirect ad- dressing. To select a specific auxiliary register, the Auxiliary Register Pointer (ARP) is loaded with a value from 0 through 7 for AR0 through AR7 respective- There are seven types of indirect addressing: auto increment, auto decrement, post indexing by either adding or subtracting the contents of AR0, single indi- rect addressing with no increment or decrement and bit reversal addressing (used in FFTs) with increment or decrement.
Page 490 Running Title—Attribute Reference 2-bit field specifying compare mode Data memory address field Format status bit Addressing mode bit Immediate operand field Port address (PA0 through PA 15 are predefined assembler symbols equal to 0 through 15 respectively). 2-bit field specifying P register output shift code 3-bit operand field specifying auxiliary register 4-bit left-shift code Internal RAM configuration bits...
Page 491 Running Title—Attribute Reference Table F–2. Instruction Set Summary ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS INSTRUCTION BIT CODE MNEMONIC MNEMONIC DESCRIPTION DESCRIPTION WORDS Absolute value of accumulator Add to accumulator with shift ADDC Add to accumulator with carry ADDH Add to high accumulator ADDK Add to accumulator short immediate ADDS...
Page 492 Running Title—Attribute Reference Table 2. Instruction Set Summary (continued) AUXILIARY REGISTERS AND DATA PAGE POINTER INSTRUCTIONS INSTRUCTION BIT CODE MNEMONIC MNEMONIC DESCRIPTION DESCRIPTION WORDS ADRK Add to auxiliary register short immediate CMPR † Compare auxiliary register with auxiliary register AR0 Load auxiliary register LARK Load auxiliary register short immediate...
Page 493 Running Title—Attribute Reference Table 2. Instruction Set Summary (continued) BRANCH/CALL INSTRUCTIONS INSTRUCTION BIT CODE MNEMONIC MNEMONIC DESCRITPION DESCRITPION WORDS Branch unconditionally BACC † Branch to address specified by accumulator BANZ Branch on auxiliary register not zero BBNZ † Branch if TC bit BBZ †...
Page 494 Running Title—Attribute Reference Table 2. Instruction Set Summary (concluded) CONTROL INSTRUCTIONS INSTRUCTION BIT CODE MNEMONIC MNEMONIC DESCRIPTION DESCRIPTION WORDS BIT † Test bit BITT † Test bit specified by T register CONF ‡ Configure RAM blocks as Data or program DINT Disable interrupt EINT...
Page 495 TMS320s as well as hands-on training with the TMS320 development tools. When technical questions arise regarding the TMS320 family, contact the Texas Instruments TMS320 Hotline at (713) 274–2320. Or, keep informed on the latest TI and third-party development support tools by accessing the DSP Bulletin Board Service (BBS) at (713) 274–2323.
Page 496 Running Title—Attribute Reference Table F–3. Software and Hardware Support MACRO ASSEMBLER/LINKER HOST COMPUTER OPERATING SYSTEMS PART NUMBER TMDS3242250-0 DEC VAX TMDS3242850-0 IBM PC MS/PS DOS TMDS3242260-0 ULTRIX TMDS3242550-0 SUN 3 UNIX C COMPILER AND MACRO ASSEMBLER/LINKER HOST COMPUTER OPERATING SYSTEMS PART NUMBER TMDS3242255-0 DEC VAX...
Page 497: Recommended Operating Conditions
V CC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments. recommended operating conditions...
Page 498 Running Title—Attribute Reference µA I OZ High-impedance-state output leakage current V CC = MAX µA Input current V I = V SS to V CC Normal V CC = MAX, f x = I CC I CC Supply current Supply current Idle/HOLD Input capacitance Output capacitance...
Page 499 Running Title—Attribute Reference CLOCK CHARACTERISTICS AND TIMING The SMJ320C26 can use either its internal oscillator or an external frequency source for a clock. internal clock option The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 2). The frequency of CLKOUT1 is one-fourth the crystal fundamental frequency.
Page 500 Running Title—Attribute Reference t d(CIH-C) CLKIN high to CLKOUT1/CLKOUT2/STRB high/low t f(C) CLKOUT1/CLKOUT2/STRB fall time t r(C) CLKOUT1/CLKOUT2/STRB rise time t w(CL) CLKOUT1/CLKOUT2 low pulse duration 2Q – 8 2Q 2Q + 8 t w(CH) CLKOUT1/CLKOUT2 high pulse duration 2Q – 8 2Q 2Q + 8 t d(C1-C2) CLKOUT1 high to CLKOUT2 low, CLKOUT2 high to CLKOUT1 high, etc.
Page 501 Running Title—Attribute Reference timing requirements over recommended operating conditions (see Note 1) UNIT t c(CI) CLKIN cycle time t w(CIL) CLKIN low pulse duration, t c(C) = 25 ns (see Note 2) t w(CIH) CLKIN high pulse duration, t c(CI) = 25 ns (see Note 2) t su(S) SYNC setup time before CLKIN low Q –...
Page 502 Running Title—Attribute Reference Figure 2. Test Load Circuit V IH (MIN) V IL (MAX) (a) Input 2.4 V V OH (MIN) 2.2 V 0.8 V V OL (MAX) 0.6 V (b) Outputs Figure 3. Voltage Reference Levels MEMORY AND PERIPHERAL INTERFACE TIMING switching characteristics over recommended operating conditions (see Note 1) PARAMETER UNIT...
Page 503 Running Title—Attribute Reference t su(D)R Data read setup time before STRB high t h(D)R Data read hold time from STRB high t d(SL-R) READY valid after STRB low (no wait states) Q – 22 Q – 22 † t d(C2H-R) READY valid after CLKOUT2 high t h(SL-R) READY hold time after STRB low (no wait states)
Page 504 Running Title—Attribute Reference NOTES: 1. Q = 1/4t c(C) 7. A15–A0, PS, DS, IS, STRB, and R/W timings are all included in timings referenced as “address.” SERIAL PORT TIMING switching characteristics over recommended operating conditions (see Note 1) PARAMETER UNIT t d(CH-DX) DX valid after CLKX rising edge (see Note 8) t d(FL-DX)
Page 505 Running Title—Attribute Reference PARAMETER MEASUREMENT INFORMATION Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.2 volts unless otherwise noted. t c(CI) t f(CI) t r(CI) X/2CLKIN t h(S) t w(CIL) t su(S) t su(S) t w(CIH)
Page 506 Running Title—Attribute Reference PARAMETER MEASUREMENT INFORMATION t d(C1-S) CLKOUT1 t d(C1-S) CLKOUT2 t d(C2-S) t d(C2-S) STRB t w(SH) t w(SL) t su(A) t h(A) A15–A0, BR, PS, DS, VALID OR IS t a(A) t su(D)R t d(SL-R) READY t h(D)R t h(SL-R) D15–D0 DATA IN...
Page 507 Running Title—Attribute Reference PARAMETER MEASUREMENT INFORMATION CLKOUT1 CLKOUT2 STRB t su(A) t h(A) A15–A0, BR, PS, DS, VALID OR IS READY t h(D)W t su(D)W D15–D0 DATA OUT t en(D) t dis(D) Figure 6. Memory Write Timing Appendix Title—Attribute Reference E-42...
Page 508 Running Title—Attribute Reference PARAMETER MEASUREMENT INFORMATION CLKOUT1 CLKOUT2 STRB A15–A0, BR PS, DS, R/W, VALID OR IS t h(C2H-R) t h(C2H-R) t d(C2H-R) t d(C2H-R) READY t h(M-R) t d(M-R) t d(M-R) D15–D0, t h(M-R) (FOR READ DATA IN OPERATION) D15–D0, (FOR WRITE OPERATION)
Page 509 Running Title—Attribute Reference PARAMETER MEASUREMENT INFORMATION CLKOUT1 t su(IN) t su(IN) t d(RS) t h(IN) t w(RS) A15–A0 FETCH LOCATION 0 D15–D0 VALID BEGIN PROGRAM EXECUTION STRB CONTROL SIGNALS † IACK SERIAL PORT CONTROLS ‡ † Control signals are DS, IS, R/W, and XF. ‡...
Page 510 Running Title—Attribute Reference Figure 8. Reset Timing CLKOUT1 STRB t su(IN) t h(IN) t w(N) INT2–INT0 t f(IN) A15–A0 FETCH N FETCH N + 1 FETCH N + 2 FETCH 1 t d(IACK) t d(IACK) IACK Figure 9. Interrupt Timing E-45...
Page 511 Running Title—Attribute Reference PARAMETER MEASUREMENT INFORMATION CLKOUT1 STRB FETCH BRANCH FETCH NEXT FETCH BIOZ ADDRESS INSTRUCTION A15–A0 PC = N PC = N + 1 PC = N + 2 PC = N + 3 OR BRANCH ADDRESS t h(IN) t su(IN) VALID Figure 10.
Page 512 Running Title—Attribute Reference PARAMETER MEASUREMENT INFORMATION CLKOUT1 CLKOUT2 STRB t d(C2H-H) (see note A) HOLD A15–A0 N + 1 N + 2 PS, DS, VALID VALID OR IS t dis(C1L-A) D15–D0 t dis(AL-A) HOLDA t d(C1L-AL) N + 1 – –...
Page 513 Running Title—Attribute Reference PARAMETER MEASUREMENT INFORMATION CLKOUT1 CLKOUT2 t en(A-C1L) STRB t d(C2H-H) (see note A) HOLD PS, DS, VALID OR IS D15–D0 t d(HH-AH) HOLDA A15–A0 N + 2 N + 2 N + 2 – – – FETCH –...
Page 514 Running Title—Attribute Reference PARAMETER MEASUREMENT INFORMATION t c(SCK) t w(SCK) t r(SCK) CLKR t h(FS) t f(SCK) t h(DR) t w(SCK) t su(FS) t su(DR) N = 8, 16 Figure 14. Serial Port Receive Timing t c(SCK) t r(SCK) t w(SCK) CLKX t w(SCK) t h(FS)
Page 515 Running Title—Attribute Reference 25,40 (1.000) 24,89 (0.980) 24,38 (0.960) MECHANICAL DATA 23,88 (0.940) FJ package leaded chip carrier package 20,52 (0.808) TOP VIEW 20,19 (0.795) PARAMETER UNIT Junction-to-free-air R θJA thermal resistance Junction-to-case R θJC thermal resistance 1,98 (0.078) 0,38 (0.015) MIN. 1,07 (0.042) 2,41 (0.095) 1,27 (0.050) NOM.
Page 516 Running Title—Attribute Reference 24, 38 (0.960) MECHANICAL DATA 23, 88 (0.940) 21,89 (0.862) MAX FD ceramic leadless (pad) chip carrier package 24, 38 (0.960) TOP VIEW 23, 88 (0.940) 21,89 (0.862) INDEX CORNER PARAMETER UNIT Junction-to-free-air R θJA 39.9 thermal resistance 20, 57 (0.810) Junction-to-case R θJC...
Page 517 Running Title—Attribute Reference 28,448 (1.120) MECHANICAL DATA 27,422 (1.080) 15,37 (0.605) 68-pin GB grid array ceramic package 28,448 (1.120) TOP VIEW 15,37 (0.605) 27,422 (1.080) PARAMETER UNIT Junction-to-free-air R θJA thermal resistance Junction-to-case R θJC thermal resistance 4,572 (0.180) 1,397 (0.055) 2,794 (0.110) 1,143 (0.045) 3,556 (0.140)
Page 518 Appendix F TMS320E25 EPROM Programming This appendix describes the TMS320E25 EPROM cell. The TMS320E25 in- corporates a 4K 16-bit EPROM, which is implemented from a standard TMS27C64 EPROM cell. This expands the capabilities of the TMS320E25 in the areas of prototyping, early field testing, and production. Key features of the EPROM cell include standard programming techniques with verification capability of all bits.
Page 519: Eprom Programming Adapter Socket
Using the EPROM Programmer Adapter Socket F.1 Using the EPROM Programmer Adapter Socket Most EPROM programmers have a 28-pin DIP-type socket for use with EPROM devices such as the TMS27C64. In order to use this type of program- mer to program a TMS320 40-pin DIP or PLCC/CLCC, you must use a special adapter that converts the programmer socket into a socket that can accept a TMS320E25 device.
Page 520: Vcc And V Pp Jumper Settings For External Power
Using the EPROM Programmer Adapter Socket Additionally, a jumper and test point are available for the V supply. The signal is a pulsed signal and fully complies with the standards for a 27C64 EPROM device. This option is never needed, and the jumpers should be left in the internal position at all times.
Page 521: Eprom Programming Data Format
TMS320E25 EPROM cell is not designed for high voltage, the cell will be damaged. To prevent an accidental application of voltage, Texas Instruments has inserted a 3.9-kΩ resistor between A9 of the TI programmer socket and the programmer itself.
Page 522: Tms320E25 Eprom Conversion To Tms27C64 Eprom Pinout
Programming and Verification Figure F–4. TMS320E25 EPROM Conversion to TMS27C64 EPROM Pinout TMS27C64 V CC TMS320E25 68 PIN (FZ) CLKIN V PP V SS Table G–1. Pin Nomenclature (TMS320E25) Signals Definition A12(MSB)–A0 (LSB) On-chip EPROM programming address lines CLKIN Clock oscillator input EPROM chip select EPROM test mode select EPROM read/verify select...
Page 523: Tms320E25 Programming Mode Levels
Programming and Verification Table G–2 shows the programming levels that are required when program- ming, verifying, and reading the EPROM cell. Following the table are individual descriptions of each programming level. Table G–2. TMS320E25 Programming Mode Levels Signal TMS320E25 TMS27C64 Program Program Read...
Page 524 Programming and Verification F.2.1 Erasure Before programming, the memory must be erased by exposing high-intensity ultraviolet light (wavelength = 2537 angstroms) into the chip through its trans- parent lid. Note that normal ambient light contains the correct wavelength for erasure. Therefore, the window should be covered with an opaque label after programming the TMS320E25.
Page 525 Programming and Verification F.2.3 SNAP! Pulse Programming The EPROM can be programmed by using the TI SNAP! pulse programming algorithm; as illustrated in the flowchart of Figure F–6, programming time is greatly reduced to a nominal duration of one second. Actual programming time varies as a function of the programmer that is being used.
Page 526: Fast Programming Flowchart
Programming and Verification Figure F–5. FAST Programming Flowchart Start Address = First Location V CC = 6 0.25 V V PP = 12.5 V 0.25 V X = 0 Program One 1-ms Pulse Increment X Fail Verify X = 25 One Byte Pass Program One...
Page 527: Snap! Pulse Programming Flowchart
Programming and Verification Figure F–6. SNAP! Pulse Programming Flowchart Start Address = First Location V CC = 6.5, V PP = 13.0 V Program Mode Program One Pulse = t w = 100 µs Increment Address Last Address? Address = First Location X = 0 Program One Pulse = t w = 100 µs Interactive...
Page 528: Programming Timing
Programming and Verification Figure F–7. Programming Timing Verify Program V IH A12–A0 Address Stable Address N+1 V IL V IH /V OH HI-Z Q8–Q1 Data In Stable Data Out Valid V IL /V OL V PP V PP V CC V CC + 1 V CC V CC...
Page 529: Tms320E25 Eprom Protect And Protect Verify Mode Levels
EPROM Protection and Verification F.3 EPROM Protection and Verification This section describes the code protection feature of the EPROM cell; an inter- nal mechanism protects the customer’s code from being illegally copied by its competitors. Table G–3 shows the programming levels required for protecting the EPROM contents and verifying that protection.
Page 530: Eprom Protection Flowchart
EPROM Protection and Verification let light, thereby maintaining security of all proprietary algorithms. Program- ming of the RBIT is accomplished by the EPROM protection cycle, which consists of setting the E, G, PGM, and A4 pins to a high level, applying 12.5 0.25 V to both V and EPT, and pulsing the Q8 pin to a low level.
Page 531: How The Rbit Fits Into The Tms320E25 Block Diagrams
This disconnect takes place at the MUX. For the TMS320E25, the internal nodes are left floating. Figure F–9 shows a portion of the TMS320C2x block diagram and includes the RBIT to show how it disconnects the external and internal program spaces.
Page 532: Eprom Protection Timing
EPROM Protection and Verification Invalid microprocessor mode. Microprocessor mode can’t be used after enabling the RBIT, because the PBUS is disconnected from the external program space. F.3.3 Protect Verify Following the EPROM protect mode, the protect verify mode reviews and veri- fies the programming of the RBIT (see Figure F–8) for accuracy.
Page 533 TMS320E25 EPROM Programming F-16...
Page 534 Appendix G Analog Interface Peripherals and Applications Texas Instruments offers many products for total system solutions, including memory options, data acquisition, and analog input/output devices. This ap- pendix describes a variety of devices that interface directly to the TMS320 DSPs in rapidly expanding applications.
Page 535: System Block Diagram
Multimedia App[lications G.1 Multimedia Applications Multimedia integrates different media through a centralized computer. These media can be visual or audio and can be input to or output from the central computer via a number of technologies. The technologies can be digital based or analog based (such as audio or video tape recorders).
Page 536: Multimedia Speech Encoding And Modem Communication
Multimedia Applications The TLC32047 wide-band analog interface circuit (AIC) is well suited for multi- media applications because it features wide-band audio and up to 25-kHz sampling rates. The TLC32047 is a complete analog-to-digital and digital-to- analog interface system for the TMS320 DSPs. The nominal bandwidths of the filters accommodate 11.4 kHz, and this bandwidth is programmable.
Page 537: Data Converter Ics
Multimedia Applications G.1.2 Multimedia-Related Devices As shown in Table H–1, TI provides a complete array of analog and graphics interface devices. These devices support the TMS320 DSPs for complete mul- timedia solutions. Table H–1. Data Converter ICs Resolution Conversion Device Description Application (Bits)
Page 538 Telecommunications Applications G.2 Telecommunications Applications The TI linear product line focuses on three primary telecommunications appli- cation areas: subscriber instruments (telephones, modems, etc.), central of- fice line card products, and personal communications. Subscriber instruments include the TCM508x DTMF tone encoder family, the TCM150x tone ringer family, the TCM1520 ring detector, and the TCM3105 FSK modem.
Page 539: Typical Dsp/Combo Interface
Telecommunications Applications Figure G–4. Typical DSP/Combo Interface TMS320C25 TCM320AC36 13 DOUT 20 kΩ Codec ANLGIN MIC_GS 20 kΩ CLKX DCLKX Codec EAR_A CLKR EAR_B V DD 1 kΩ DCLKR 1 kΩ ENP ENT ENP ENT 2.048 MHz 74S161 74S161 390 Ω 390 Ω...
Page 540: Dsp/Combo Interface Timing
Table H–3 are contained in the 1991 Telecommunications Circuits Databook (literature number SCTD001B). To request your copy, contact your nearest Texas Instruments field sales office or call the Literature Response Center at (800) 477–8924. For further information on these telecommunications products, please call TI...
Page 541: Telecom Devices
Telecommunications Applications Table H–3. Telecom Devices Coding Clock Rates Device Number # of Bits Comments † Codec/Filter µ TCM29C13 A and 1.544, 1.536, 2.048 C.O. and PBX line cards µ TCM29C14 A and 1.544, 1.536, 2.048 Includes 8th-bit signal µ TCM29C16 2.048 16-pin package...
Page 542: General Telecom Applications
Telecommunications Applications Figure G–6. General Telecom Applications Analog Neighborhood Cellular Phones Concentrator Phone TCM29C23 Combo HVLI/HCombo TCM5087 Tone TMS320xx DSP TCM1060/1030 TCM5089 Encoder TGAP90x Cell Base TCM5092 TCM320AC3X VBAP Combo TCM5094 Station TCM153x Ringer TGAP901 Answering Machine Central Office Toll Office TCM1520 Detector TSP50C1x Speech Synthesis TCM29C13 Combo...
Page 543: Voice Synthesizers
16K–32K TI has low-cost memories that are ideal to use with speech synthesis chips. Texas Instruments can also be of assistance in developing and processing the speech data that is used in these speech synthesis systems. Table H–6 shows speech memory devices of different capabilities. Additionally, audio filters are outlined in Table H–7.
Page 544: Switched-Capacitor Filter Ics
Dedicated Speech Synthesis Applications Table H–7. Switched-Capacitor Filter ICs Device Function Order Roll-Off Power Out Power Down TLC2470 Differential audio filter amplifier 5 kHz 500 mW TLC2471 Differential audio filter amplifier 3.5 kHz 500 mW TLC10/20 General-purpose dual filter TLC04/14 Low pass, Butterworth filter Speech Synthesis Development Tools Software:...
Page 545: Generic Servo Control Loop
Servo Control/Disk Drive Applications G.4 Servo Control/Disk Drive Applications Several years ago, most servo control systems used only analog circuitry. However, the growth of digital signal processing has made digital control theory a reality. Figure G–8 shows a block diagram of a generic digital control system using a DSP, along with an ADC and DAC.
Page 546: Disk Drive Control System Block Diagram
Servo Control/Disk Drive Applications Figure G–9 shows a block diagram of a disk drive control system. Figure G–9. Disk Drive Control System Block Diagram SCSI Data Buffer Control SCSI Data Host Interface Buffer Separator Data Sequencer Control Disk Drive Motor EPROM Servo Controller...
Page 547: Tms320C14 - Tlc32071 Interface
Servo Control/Disk Drive Applications Figure G–10 shows the interfacing of the TMS320C14 and the TLC32071. Figure G–10. TMS320C14 – TLC32071 Interface D0–D7 CSCNTRL CSAN Address Decode Logic RESET TMS320C14 TLC32071 For further information on these servo control products, please call TI Linear Applications at (214) 997–3772.
Page 548: Modem Afe Data Converters
Modem Applications G.5 Modem Applications High-speed modems (9,600 bps and above) require a great deal of analog sig- nal processing in addition to digital signal processing. Designing both high- speed capabilities and slower fall-back modes poses significant engineering challenges. TI offers a number of analog front-end (AFE) circuits to support various high-speed modem standards.
Page 549: High-Speed V.32 Bis And Multistandard Modem With The Tlc320Ac01 Aic
Modem Applications For further information or application assistance, please call TI Linear Applica- tions at (214) 997–3772. Figure G–11. High-Speed V.32 Bis and Multistandard Modem With the TLC320AC01 AIC TLC320AC01 – ADC and DAC Fine Tune Echo-Cancel Telephone TMS320C25/C5x Line Echo Canceler Transmitter Serial...
Page 550 Modem Applications Lower TLC320AC01 D/A Path: Converts the upper TMS320C25 transmit output to an analog signal, performs a smoothing filter function, and drives the DAC. Lower TLC320AC01 D/A Path: Converts the echo-free receive signal to a digital signal, which is sent to the lower TMS320C25 to be decoded.
Page 551: Applications Performance Requirements
Advanced Digital Electronics Applications for Consumers G.6 Advanced Digital Electronics Applications for Consumers With the extensive use of the TMS320 DSPs in consumer electronics, much electromechanical control and signal processing can be done in the digital do- main. Digital systems generally require some form of analog interface, usually in the form of high-performance ADCs and DACs.
Page 552: Video Signal Processing Basic System
Advanced Digital Electronics Applications for Consumers Figure G–13. Video Signal Processing Basic System TMS320 TV IF Buffer Amplifier Video Signal System Field Controller Memory Clock Generator VCRs, compact disc and DAT players, and PCs are a few of the products that have taken a major position in the marketplace in the last ten years.
Page 553: Audio/Video Analog/Digital Interface Devices
Advanced Digital Electronics Applications for Consumers The audio processing becomes more demanding as higher fidelity is required. Better fidelity translates into lower noise and distortion in the output signal. The TMS57013DW/57014DW 1-bit digital-to-analog converters (DAC) in- clude an 8 times over sampling digital filter designed for digital audio systems, such as CDPs, DATs, CDIs, LDPs, digital amplifiers, car stereos, and BS tun- ers.
Page 554 Memories, Analog Converters, Sockets, and Crystals This appendix provides product information regarding memories, analog con- verters, and sockets, which are manufactured by Texas Instruments and are compatible with the TMS320C2x. Information is also given regarding crystal frequencies, specifications, and vendors.
Page 555 This section provides product information for EPROM memories, codecs, ana- log interface circuits, and A/D and D/A converters. All of these devices can be interfaced with TMS320C2x processors (see Chapter 6 for hardware interface designs). Refer to Digital Signal Processing Applications with the TMS320 Family for additional information on interfaces using memories and analog conversion devices.
Page 556 Sockets H.2 Sockets The sockets produced by Texas Instruments are designed for high-density packaging needs. The production sockets and burn-in/test sockets for PGA, PLCC, and CER-QUAD packages are compatible with the TMS320C2x devices. For additional information about TI sockets, contact the nearest TI sales office Texas Instruments Incorporated Connector Systems Dept, M/S 14–3...
Page 557: Crystal Connection
Crystals H.3 Crystals This section lists the commonly used crystal frequencies, crystal specification requirements, and the names of suitable vendors. Table I–1 lists the commonly used crystal frequencies and the devices with which they can be used. Table I–1. Commonly Used Crystal Frequencies Device Frequency TMS320C25...
Page 558 Crystals Vendors of crystals suitable for use with TMS320 devices are listed below. RXD, Inc. Norfolk, NB (800) 228–8108 N.E.L. Frequency Controls, Inc. Burlington, WI (414) 763–3591 CTS Knight, Inc. Contact the local distributor.
Page 559 Memories, Analog Converters, Sockets, and Crystals...
Page 560 ROM Codes The size of a printed circuit board must be considered in many DSP applica- tions. To fully utilize the board space, Texas Instruments offers two options that reduce the chip count and provide a single-chip solution to its customers.
Page 561: Tms320 Rom Code Flowchart
— TMS320 New Code Release Form — Print Evaluation and Acceptance Form (PEAF) — Purchase Order for Mask Charge Prototypes — TMS320 Code Texas Instruments Responds: — Customer Code Input into TI System — Code Sent Back to Customer for Verification Customer...
Page 562 Modem (BBS): TI-tagged or COFF format from cross-assembler When a code is submitted to Texas Instruments for masking, the code is refor- matted to accommodate the TI mask generation system. System-level verifi- cation by the customer is therefore necessary. Although the code has been re- formatted, it is important that the changes remain transparent to the user and do not affect the execution of the algorithm.
Page 563 ROM Codes...
Page 564 Product quality and reliability monitoring. Our customer’s perception of quality must be the governing criterion for judg- ing performance. This concept is the basis for Texas Instruments Corporate Quality Policy, which is as follows: “For every product or service we offer, we shall define the requirements that solve the customer’s problems, and we shall conform to those requirements...
Page 565 Reliability Stress Tests J.1 Reliability Stress Tests Accelerated stress tests are performed on new semiconductor products and process changes to ensure product reliability excellence. The typical test envi- ronments used to qualify new products or major changes in processing are: High-temperature operating life Storage life Temperature cycling...
Page 566 Reliability Stress Tests Table K–1 lists the microprocessor and microcontroller reliability tests, the duration of the test, and sample size. The following terms define or describe these tests: AOQ (Average Outgoing Quality) Amount of defective product in a population, usu- ally expressed in terms of parts per million (PPM).
Page 567 Reliability Stress Tests Mechanical Sequence: Fine and gross leak Per MIL-STD-883C, Method 1014.5 Mechanical shock Per MIL-STD-883C, Method 2002.3, 1500g, 0.5 ms, Condition B PIND (optional) Per MIL-STD-883C, Method 2020.4 Vibration, variable frequency Per MIL-STD-883C, Method 2007.1, 20g, Condition A Constant acceleration Per MIL-STD-883C, Method 2001.2, 20 kg, Condition D, Y1 Plane min...
Page 568: Microprocessor And Microcontroller Tests
– Thermal impedance † If junction temperature does not exceed plasticity of package. Table K–2 provides a list of the TMS320C2x devices, the approximate number of transistors, and the equivalent gates. The numbers have been determined from design verification runs.
Page 569 Quality and Reliability...
Page 570: Development Support
Evaluation module (EVM) In-circuit emulator (XDS/22) Analog interface board (AIB2) Each TMS320C2x support product is described in the TMS320 Family Devel- opment Support Reference Guide (literature number SPRU011C). In addition, more than 100 TMS320 third-party developers provide support products to complement TI’s offering.
Page 571 Device and Development Support Tool Nomenclature Device and Development Support Tool Nomenclature To designate the stages in the product development cycle, Texas Instruments assigns prefixes to the part numbers of all TMS320 devices and support tools. Each TMS320 member has one of three prefixes: TMX, TMP, and TMS. Texas Instruments recommends two of three possible prefix designators for its sup- port tools: TMDX and TMDS.
Page 572: Tms320 Device Nomenclature
Device and Development Support Tool Nomenclature Figure K–1.TMS320 Device Nomenclature TMS 320 C 25 GB L PREFIX TEMPERATURE RANGE TMX = experimental device 0 to 50 C TMP = prototype device 0 to 70 C TMS = qualified device S = -55 to 100 C SMJ = MIL–STD–883C M = -55 to 125 C A = -40 to 85 C...
Page 573: Tms320 Development Tool Nomenclature
Device and Development Support Tool Nomenclature Figure K–2 provides a legend for reading the part number for any TMS320 hardware or software development tool. Figure K–2.TMS320 Development Tool Nomenclature TMDS 32 4 28 1 0 – 0 2 MEDIUM † QUALIFICATION STATUS TMDX = prototype 2 = 5-1/4”...
Page 574 Index Index analog interface peripherals advanced digital applications, G-18–G-20 audio/video analog/digital interface devices, G-20 A/D interface, 6-43–6-45 digital audio, G-19 A-law, 5-68 video signal processing, G-19 ABS, 4-23 applications, G-1–G-20 disk drive applications, G-12–G-14 ACC, 3-9 modem applications, G-15–G-17 accumulator, 3-9, 3-30 data converters, G-15 carry bit, 3-31 multimedia, G-2–G-4...
Page 575 Index ARAU, 3-9 ARB, 3-9 B, 4-42 architectural overview, 3-2 BACC, 4-43 arithmetic logic unit (ALU), 3-3 BANZ, 4-44 diagram, 3-3 BBNZ, 4-46, 5-45 direct memory access, 3-5 memory interface, 3-4 BBZ, 4-47, 5-45 multiplier, 3-3 BC, 4-48 multiprocessing, 3-4 BGEZ, 4-49 on-chip memory, 3-2 BGZ, 4-50...
Page 576 Index bootloader (continued), 5-6–5-21 companding, 5-68 serial download, 5-11–5-15 comparison of internal RAM, 3-18 program length, 5-14 computed GOTO, 5-28 RS232 serial link, 5-11 CONF, 4-77 RS232 transfer protocol, 5-12 RS232 transfer sequence, 5-13 configuring on-chip RAM, 5-35–5-37 software listing, 5-17–5-21 diagram, 5-36 types of download, 5-6 example, 5-37, 5-39...
Page 577 Index development systems, K-1 EPROM programming, F-1 analog interface board (AIB2), K-1 code protection, F-12–F-15 emulator (XDS/22), K-1 data format, F-4 evaluation module (EVM), K-1 erasure, F-7 simulator, K-1 FAST programming, F-7, F-9 output disable, F-11 development tool nomenclature, K-4 pin nomenclature, F-5 device evolution, K-2 program inhibit, F-11...
Page 578 Index Fourier transforms, 5-75 immediate addressing, 4-8–4-10 framing control, 3-67 IMR, 3-10, 3-60 FSR, 2-7 IN, 4-84, 5-34 FSX, 2-7 indexed addressing, 5-62 functional block diagram, 3-6–3-8 indirect addressing, 4-4–4-8 arithmetic operations, 4-6 bit fields, 4-7 diagram, 4-4 format examples, 4-8 gates, J-5 symbols used, 4-5 global memory, 3-76, 6-35...
Page 579 Index instruction set (continued), 4-11 instruction set (continued), 4-11 BNC, 4-64 OUT, 4-131 BNV, 4-65 PAC, 4-132 BNZ, 4-66 POP, 4-133 BV, 4-67 POPD, 4-134 BZ, 4-68 PSHD, 4-135 CALA, 4-69 PUSH, 4-136 CALL, 4-71 RC, 4-137 RET, 4-138 CMPL, 4-73 CMPR, 4-74 RFSM, 4-139 CNFD, 4-75...
Page 580 Index instruction set (continued), 4-11 interrupts, 2-5, 3-46, 3-59–3-62 TBLR, 4-184 external interface, 3-60 TBLW, 4-186 locations, 3-59 TRAP, 4-188 logic diagram, 3-61 XOR, 4-189 operation, 3-59 XORK, 4-190 priorities, 3-59, 5-32 ZAC, 4-191 timing diagram, 3-62 ZALH, 4-192 IR, 3-10 ZALR, 4-193 IS, 2-4 ZALS, 4-194...
Page 581 Index multimedia applications, G-2 multimedia-related devices, G-8 µ-law, 5-68 multiplexed external data bus, 3-42 multiplication, 5-53–5-57 MAC, 4-111 ’C25, 5-66 MACD, 4-114 multiplier, 3-3, 3-10, 3-32 MACD operation, 5-52 multiprocessing, 3-75–3-81 MAR, 4-117 global memory, 3-76 masked parts, I-1 hold function, 3-78–3-81 MCS, 3-10 synchronization, 3-75 memories, H-2...
Page 582 Index PFC, 3-10 PIC, ix QIR, 3-10 PID control, 5-82 quality and reliability, J-1–J-5 pin assignments, 2-2 queue instruction register, 3-10 pinouts, 2-1 pipeline hardware, 3-45 pipeline operation, 3-37–3-47 ADD followed by SACL, 3-41 R/W, 2-5 branch to on-chip RAM, 3-44 RAM(B0), 3-10 ’C25, 3-39 RAM(B1), 3-10...
Page 583 Index ROVM, 4-143 short immediate addressing, 4-9 RPT, 4-144, 5-27 signal descriptions, 2-4–2-7 single-instruction loops, 5-26 RPTC, 3-10 SMJ320C2x, data sheets, D-1 RPTK, 4-9, 4-145 SNAP! pulse programming, F-8 RS, 2-6 flowchart, F-10 RSR, 3-11 sockets, H-3 RSXM, 4-146 software stack, 5-24 RTC, 4-147 software stack expansion, 5-24 RTXM, 4-148...
Page 584 6-51 TMS320C26 description, instrumentation, 6-51 TMS320C28, 1-1–1-7, 2-3, modem, 6-48 data sheet, C-1 numeric processing, 6-51 TMS320C2x, instruction cycle timings, E-2 voice coding, 6-49 TMS320C2x block diagram, 3-7 system control, 3-35–3-53 TMS320E25, 1-4 See also control circuitry TR, 3-11 ’C25 powerdown modes, 3-53...
Page 585 Index X1, 2-6 ZAC, 4-191 X2/CLKIN, 2-6 ZALH, 4-192 XDS/22, K-1 ZALR, 4-193 XF, 2-6, 3-56 ZALS, 4-194 XOR, 4-189 XORK, 4-9, 4-190 XSR, 3-11 Index-12...
Page 586 Running Title—Attribute Reference IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current.

Texas Instruments TMS320C2x User Manual

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