Block Diagram - Hdmi Sw Section - Sony STR-DG910 Service Manual

STR-DG910
Q Q
3 7 6 3 1 5 1 5 0
5-4. BLOCK DIAGRAM — HDMI SW SECTION —
SWITCHER
IC3503
SDA_SINK 39
1
DATA2+
58 A34
3 DATA2–
57 B34
SCL_SINK 38
DATA1+
4
55 A33
6 DATA1–
54 B33
7 DATA0+
52 A32
DATA0–
9
51 B32
CN3501 10 CLOCK+
49 A31
SAT IN 12 CLOCK–
48 B31
13
CEC
15
SCL(5V)
46 SCL3
SDA(5V)
16
45 SDA3
18
+5V POWER
19 HOT PLUG DET
44 HPD3
1
DATA2+
Y1 34
77 A24
3
DATA2–
Z1 35
76 B24
4
DATA1+
Y2 31
74 A23
6
DATA1–
32
Z2
73 B23
7
DATA0+
Y3 28
71 A22
9
DATA0–
Z3 29
70 B22
CN3502 10
CLOCK+
Y4 25
68 A21
HDMI DVD IN 12
CLOCK–
Z4 26
67 B21
13
CEC
15
SCL(5V)
64 SCL2
16 SDA(5V)
63 SDA2
18
+5V POWER
19 HOT PLUG DET
T E
L 1 3 9 4 2 2 9 6 5 1 3
62 HPD2
1 DATA2+
15
A14
3
DATA2–
14 B14
4 DATA1+
12 A13
6 DATA1–
11 B13
7
DATA0+
9
A12
9 DATA0–
8 B12
CN3503
10 CLOCK+
6 A11
VIDEO 2/BD
12
CLOCK–
5
B11
IN
13 CEC
15
SCL(5V)
3 SCL1
HPD_SINK 40
SDA(5V)
16
2 SDA1
21
+5V POWER S1
18
S2 22
19 HOT PLUG DET
80
HPD1
S3 23
42
XOE
POWER DETECT
IC3501 (1/2)
1 3
+5V REG
5 6
Q305–307
9 8
w w w
STR-DG910
DATA BUFFER
EEPROM DATA SELECT EEPROM
IC3507
IC3521 IC3509
3 SDAA SDAB 6 5
3
5 SDA
1
2 SCLA SCLB 7 14
13
6 SCL
12
WP
10 7
HDMI RX
IC3511
92-96
99-105
QE23
108-111
41 DSDA I
114-117
QE0
119,
42 DSDL
121-124
VSYNC 1
51 RXC+
HSYNC 128
50 RXC–
DE 127
55 RXO+
54 RXO–
59 RX1+
70
SPDIF
58 RX1–
WS 75
63 RX2+
SCK 76
62 RX2–
MCLK 79
SD3 71
84 XTALOUT
I I
X3501
SD0 74
28.322MHz
85 XTALIN
CSDA 39
CSCL 40
44 PWR5V
91 INT
89 RESET
MUTE 67
28 27
CSDA CSCL
19 RX_RST
TX_5VPWR 41
20 RX_INT
TX_RST 42
35
EEPROMSEL1
43
TX_INT
XOUT
11
X3502
10MHz
13 XIN
HDMI CONTROL
65
21 RX_HPDI MUTE
IC3519
51 TMDS_S1 TX 33
RX 34
52 TMDS_S2
53 TMDS_S3
54 TMDS_OEB
RESET 10
55 P5V_SELA
232_OUT 29
56 P5V_SELB
232_IN 30
CNVSS 7
66 67 68 69 70
3
2
B
9
4
10
HDMI+1.8V
A
5
POWER SELECT
IC3504 HDMI+1.8V2
x a o
HDMI+1.8V3
y
. i
HDMI+2.5V
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8
MUTE ERROR
SPDIF
VIDEO
LRCK
DIGITAL
H SECTION
BCK
SECTION
(Page 19)
MCK
(Page 18)
SD0–SD3
HDMI TX
IC3513
DATA2+
TX2+ 36
DATA2–
D23
49-58 35
TX2–
61-70 I DATA1+
TX1+ 33
75-79
D0
DATA1–
TX1– 32
DATA0+
TX0+ 30
2 VSYNC
DATA0–
TX0– 29
1 HSYNC
CLOCK+
TXC+ 27
80 DE
CLOCK–
TXC– 26
5
SPDIF
SCL(5V)
20
DSCL DATA BUFER
11 WS SDA(5V)
Q3504
DSDA 19
12 SCK
6 MCLK
POWER
7 SD3
+5V POWER
CONTROL
5 4
I I +6.3V
IC3516
10 SD0
1
44 CSDA
Q Q
POWER DETECT
3 7 6 3
43 CSCL
IC3501 (2/2)
HOT PLUG DET
66 IDCK HPD 18
11 12
17
INT
42
RESET
SYSTEM CONTROL
IC1010 (4/7)
30 HDMI_ERR CEC BUFFER
CEC OUT 29
Q1103–1106
102 FLASH_SO/HDMI_UART_TX
103 FLASH_SO/HDMI_UART_RX
HDMI RESET 104
HDMI+3.3V
+3.3V REG
4 2 +4.1V
HDMI+3.3V
IC3526
+1.8V REG
+3.3V REG
3 1 4 2
IC3528
IC3527
+3.3V REG
+1.8V REG
3 1 3 1
IC3807
IC3808
HDMI+3.3V2
+1.8V REG +3.3V REG
u 1 6 3
4 5 3 1
IC3805
IC3806
HDMI+3.3V3
.
+2.5V REG
+3.3V REG
4 2 3 1
IC3816
IC3815
1
HDMI+3.3V4
HDMI+3.3V5
20 20
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2 4
9 9 8
INTERGRATED MULTI-FORMAT
SDTV/HDTV VIDEO DECODER AND
RGB GRAPHICS DIGITIZER
IC3801
X3801
28.63636MHz
CR IN 72 AIN4
38
X TAL
74 AIN5
CB IN
SCAN CONVERTER
I
AIN6
76
CY IN
SOY
77
36 2
LLC1
AIN11
CVBS IN 73
V0/Y0
7–10
AD_INT
I
3 INT
91–94
V7/Y7
AD_RST
RESET
78
99 22,23,25-28
81 82 4
41,42
15
1
16
3
135
4
136
6
7
9
10
12
CN3504
HDMI P12–19 7–14
15
D2,3,6–23
16
41–45
OUT
Y2–9
BUS SWITCH 48–50
IC3802,3811–3814
H SYNC
58–60
CBY2–9
18
63–67
V SYNC
ODCK
IP_HSYNC
21
IP_VSYNC
20
IP_DCK
1 5 1 5 0 8 9 2 4
40
19
13 4
CEC
137
CN3510
2
RESET
3
232_OUT
5
232_IN
1
CNVSS
3.3V
7
m
c o
2
9 9
PROGRESSIVE
IC3803 HDMI SDRAM
IC3804
CLKI
110–113 2,3,5,6
MD0 116–119 8,9,11,12 DQ0
I I
122–125 39,40,42,43
MD15 DQ15
129–132 45,46,48,49
MA0 80–83 21–24
A0
I
86–89 27–32 I
MA11
A11
94–97 19,20
NHSI
WE 104 15 WE
NVSI
MCLK 103 35 CLK
SDA
CAS 102 16 CAS
SCL
CKEDQE 101 14
DQML
36 DQMU
RAS 100
17 RAS
P12–19
V02
I
Y09
C02
I
C09
NHSO
NVSO
9 8 2 9 9
CLKO
PLL_EN
SRN