Yamaha CDR1000 Service Manual page 13

HD64F3039F18 (XW700A00) CPU
PIN NO. NAME I/O FUNCTION
1 TIOCA3 I/O
2 TIOCB3 I/O
3 TIOCA4 I/O Input capture/output compare
4 TIOCB4 I/O
5 TOCXA4 I/O
6 TOCXB4 I/O
7 MD2 I Mode control
8 /ADTRG/TP15/PB7 AD conversion external trigger input
9 TXD0/P90 O Transmit data
10 RXD0/P92 I Receive data
11 /IRQ4/SCK0/P94 I
Interrupt request
12 VSS - Ground
13 D0/P30 I/O
14 D1/P31 I/O
15 D2/P32 I/O
16 D3/P33 I/O Data bus
17 D4/P34 I/O
18 D5/P35 I/O
19 D6/P36 I/O
20 D7/P37 I/O
21 VCC - Power supply
22 A0/P10 O
23 A1/P11 O
24 A2/P12 O
25 A3/P13 O Address bus
26 A4/P14 O
27 A5/P15 O
28 A6/P16 O
29 A7/P17 O
30 VSS - Ground
31 A8/P20 O
32 A9/P21 O
33 A10/P22 O
34 A11/P23 O
35 A12/P24 O Address bus
36 A13/P25 O
37 A14/P26 O
38 A15/P27 O
39 A16/P50 O
40 A17/P51 O
PIN NO. NAME I/O FUNCTION
41 A18/P52 O Address bus
42 A19/P53 O
43 P60//WAIT I Wait
44 MD0 I Mode control
45 MD1 I
φ
46 O System clock
47 /STBY I Standby
48 /RES I Reset
49 NMI Non-maskable interrupt
50 VSS Ground
51 EXTAL I
Crystal oscillator
52 XTAL I
53 VCC Power supply
54 P63/AS O Address strobe
55 P64/RD O Read
56 P65/WR O Write
57 /RESO/FWE I/O Reset output/write enable signal
58 AVSS - Ground
59 P70/AN0 I
60 P71/AN1 I
61 P72/AN2 I
62 P73/AN3 I
Analog input
63 P74/AN4 I
64 P75/AN5 I
65 P76/AN6 I
66 P77/AN7 I
67 AVCC - Power supply
68 P80//IRQ0 I Interrupt request
69 P81//IRQ1 I
70 P91/TXD1 O Transmit data
71 P93/RXD1 I Receive data
72 P95/SCK1/IRQ5 I Interrupt request
73 PA0/TP0/TCLKA I
74 PA1/TP1/TCLKB I Clock input
75 PA2/TP2/TIOCA0/TCLKC I
76 PA3/TP3/TIOCB0/TCLKD I
77 A23 O
78 A22 O Address bus
79 A21 O
80 A20 O
SM5844AF (XW097A00) Sample Converter
PIN
NAME I/O FUNCTION
NO.
1 DI I Input data
2 DI I
3 BCKI I Input side bit clock
4 BCKI I
5 LRCI I Input side word clock
6 ICLK I Input side system clock input
7 ICKSL I Input side system clock select
8 IFM1 I Input format setting
IMF1 IMF2 Word length Data sequence Data position
9 IFM1 I
L L 16 Bit MBS first Stuffs back
10 IFM2 I L H 20 Bit MSB first Stuffs back
H L 20 Bit MSB first Stuffs ahead
11 IFM2 I H H 20 Bit LSB first Stuffs back
12 VDD - Power supply
13 VDD -
14 DMUTE I
Mute
15 DMUTE I
16 MCOM I 17 to 20 pin control select
MCDM H: data input
17 MDT/FSI1 I
L: de-emphasis clock select
MCDM H: Bit clock of data input
18 MCK/FSI2 I
L: de-emphasis clock select
19 I MCDM H: data word latch clock
MLEN/DEEM
20 I L: de-emphasis on/off control
MLEN/DEEM
21 OW18N I Output format setting*1
22 OW18N I
*1 IISN: H
Output format OW20N
16 bit H
18 bit Stuffs back H
L
20 bit
L
Stuffs ahead
IISN: L
Output format OW20N
16 bit H
18 bit H
IIS MODE
Stuffs ahead L
20 bit
L
CDR1000
PIN
NAME I/O FUNCTION
NO.
23 OW20N I Output format setting*1
24 OW20N I
25 IISN I IIS output mode select
26 IISN I H: normal L: IILS
27 STATE O
Output which shows internal operation
28 TST1N I Diza ON/OFF select
29 TST2N I Test
30 RSTN I Reset
31 RSTN I
32 VSS - Ground
33 VSS -
34 SLAVE I Mode select of BCKO and LRCO
35 SLAVE I H: input L: output
36 THRUN I
Slue mode setting of DOUT
37 THRUN I
38 OCKSL I Output side system clock select
39 OCLK I Output side system clock input
Output side word clock input/output
40 LRCO I/O
41 BCKO I/O Output side Bit clock input/output
42 BCKO I/O
43 DOUT O Data Out
44 DOUT O
OW18N
H
L
H
L
OW18N
H
L
H
L