Denon adv-m71 Service Manual page 11
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Also See for adv-m71:
- Operating instructions manual (340 pages) ,
- Specifications (2 pages) ,
- Specifications (2 pages)
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Pin No.
Pin Name
24
RESET#
25
TDMDX
28
TDMDR
29
TDMCLK
30
TDMFS
31
TDMTSC#
TWS
SEL_PLL2
32
TSD0
33
SEL_PLL0
TSD1
36
SEL_PLL1
37
TSD[2]
38
TSD[3]
39
MCLK
40
TBCK
TE
L 13942296513
SPDIF
SEL_PLL3
41
42,48
NC
45
RSD
46
RWS
47
RBCK
49
XIN
50
XOUT
51
AVEE
66:61, 58:53
DMA[11:0]
69
DCAS#
70
DSCK_EN
71
DWE#
72
DRAS#
73
DMBS0
74
DMBS1
96:93, 90:85,
DB[15:0]
82:77
97, 100
DCS[1:0]#
101
DQM
102
DSCK
105
DCLK
106
UDAC
www
107
VREF
108
CDAC
109
COMP
110
RSET
.
111
ADVEE
113
YDAC
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I/O
I
Reset input, active low.
O
TDM transmit data.
I
TDM receive data.
I
TDM clock input.
I
TDM frame sync.
O
TDM output enable.
O
Audio transmit frame sync.
I
System and DSCK output clock frequency selection is made at the rising edge of RESET#.
The matrix below lists the available clock frequencies and their respective PLL bit settings.
SEL_PLL2
0
0
0
0
1
1
1
1
O
Audio transmit serial data port 0.
I
Refer to the description and matrix for SEL_PLL2 pin 32.
O
Audio transmit serial data port 1.
I
Refer to the description and matrix for SEL_PLL2 pin 32.
O
Audio transmit serial data output 2.
O
Audio transmit serial data output 3.
I/O
Audio master clock for audio DAC.
O
Audio transmit bit clock.
O
S/PDIF output.
I
Clock source select.
SEL_PLL3
0
1
No connect pins. Leave open.
I
Audio receive serial data.
I
Audio receive frame sync.
I
Audio receive bit clock.
I
Crystal input.
O
Crystal output.
I
Analog power for PLL.
O
DRAM address bus [11:0]
O
DRAM column address strobe,
O
DRAM clock enable.
O
DRAM write enable.
O
DRAM row address strobe.
O
SDRAM bank select 0.
O
SDRAM bank select 1.
I/O
DRAM data bus [15:0]
O
SDRAM chip select [1:0]
O
Data input/output mask.
O
Output clock to SDRAM.
I
27 MHz clock input to PLL.
O
Video UDAC output.
I
Internal voltage to video DAC.
O
Video CDAC output.
x
ao
u163
y
I
Compensation input.
i
I
DAC current adjustment resistor input.
I
Analog power for video DAC.
O
Video YDAC output.
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2 9
8
Function
SEL_PLL1
SEL_PLL0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Q Q
3
6 7
1 3
1 5
Clock Source
Crystal oscillator
DCLK input
co
.
11
ADV-M71
9 4
2 8
Clock Type
VCO off.
DCLK
Bypass mode
DCLK x 2
DCLK x 4.5
DCLK x 3
DCLK x 3.5z
DCLK x 4
0 5
8
2 9
9 4
2 8
m
11
9 9
9 9
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