Omega OME-PIO-D144 Hardware Manual page 13

Pci-bus digital i/o board
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Example 3: assume CN1_PC0 is initial Low, active High,
As follows:
CN1_PC0
CN1_PC1
CN1_PC2
CN1_PC3
CN1_PC0 &
CN1_PC1 are
active at the same
time.
CN1_PC2 &
CN1_PC3 are
active at the same
time.
Refer to DEMO5.C for source program. All these four falling-edge & rising-edge
can be detected by DEMO5.C.
Note: When the interrupt is active, the user program has to identify the active
signals. These signals maybe all active at the same time. So the interrupt
service routine has to service all active signals at the same time.
OME-PIO-D144 User's Manual (Ver.2.1, Sep/2001)
CN1_PC1 is initial High, active Low
CN1_PC2 is initial Low, active High
CN1_PC3 is initial High, active Low
CN1_PC0 &
CN1_PC1 are
return to normal
at the same time.
CN1_PC2 &
CN1_PC3 are
return to normal
at the same time.
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