Table of Contents
Advertisement
D[0..7]
: BIDIR;
DUMMY
: BIDIR;
)
VARIABLE
Bcsr0[0..SIZE0],
Bcsr1[0..SIZE1],
Bcsr4[2..SIZE4],
Bcsr5[0..SIZE5],
Bcsr6[0..SIZE6],
WE0Spare,
HOST_EN,
SyncHardReset,
DSyncHardReset,-- Double D-ff to double synchronize the HRESET input.
FlashOE,
SyncTEA
Data_Buff[0..SIZE0]
: TRI;
DivEn,
-- WDEn,
StartStopWD
: SRFF;
HRESET_FEdge
: lpm_counter WITH (LPM_WIDTH = 2, LPM_DIRECTION = "UP");
SoftRstMachin,
AbortRstMachin,
HardRstMachin
: Reset_Ensure;
HRD_SHIFT
: lpm_shiftreg WITH (LPM_WIDTH = SHIFT_LENGTH);
DATA_HOLD
: lpm_counter WITH (LPM_WIDTH = 2, LPM_DIRECTION = "UP");
% The Reset Ensure Code disables the debouncing of all 3 reset push buttons
in case of 3 msec bouncing time (Equal count is 2^19)%
ResetEnsure
: lpm_counter WITH (LPM_WIDTH = 19, LPM_DIRECTION = "UP");
PRST_Ensure
% Provide Altera safe Power-on-Reset to initiate BCSR4 register %
EE0_HOLD
% Hold EE0 in high up to X clocks after HRESET becomes disasserted to enter the chip
into the debug mode%
EE45_HOLD
% Hold EE4,EE5 setting up to X clocks after SRESET becomes disasserted for correct boot %
POR_IMPULSE1,
POR_IMPULSE2,
WD_TIMER1,
WD_TIMER2,
WD_TIMER3,
WD_TIMER4,
WD_TIMER5,
WD_TIMER6,
WD_TIMER7,
WD_TIMER8
: freqdiv; -- Dividers to provide PONRESET pulse from Clock Osc
SM73288X,
SM73248X,
SM73228X,
FLASH_BANK1,
FLASH_BANK2,
FLASH_BANK3,
FLASH_BANK4,
FIRST_CFG_BYTE_READ,
MOTOROLA
Freescale Semiconductor, Inc.
-- Bidirectional 8-bit wide Data Bus
-- Blank - Schematic's bug workaround
-- BCSR4 is utilized for MODCK reconfig - Service Register 1
-- BCSR5 is utilized to program synthesizer - Service Register 2
-- BCSR6 is utilized to program synthesizer - Service Register 3
--
*** Option ***
-- optional Flash OE (BPOEb)
-- optional cell for TEA~ line
: DFF;
-- Starter for divider to produce PONRESET pulse from clock
-- Starter for divider to produce WD
-- Control WD
--State Machines for Push Buttons
: lpm_counter WITH (LPM_WIDTH = 5, LPM_DIRECTION = "UP");
: lpm_counter WITH (LPM_WIDTH = 12, LPM_DIRECTION = "UP");
: lpm_counter WITH (LPM_WIDTH = 10, LPM_DIRECTION = "UP");
-- First 4 bit Stage
-- Second 4 bit Stage
-- WD first 4 bit stage
-- WD second 4 bit stage
-- WD third 4 bit stage
-- WD forth 4 bit stage
-- WD fifth 4 bit stage
-- WD sixth 4 bit stage
-- WD seventh 4 bit stage
-- WD eighth 4 bit stage
-- Flash Devices available
MSC8101ADS RevB User's Manual
For More Information On This Product,
Go to: www.freescale.com
C-105
Advertisement
Table of Contents
