Onyx Dr Board Block Diagram - Panasonic GP6DU Technical Manual

ONYX DR Board Block Diagram

Figure 15 - DR Board Block Diagram
RGB signals output by the receiver box are input to the DR board via pins 1, 2, and 3 of
the socket CN3300. Upon entry to the DR-board, these signals are buffered by the
transistors Q3300, Q3301, and Q3302 and then output to IC3309 for video input
selection.
Video signals, from the receiver box, are also applied via the connector CN3301, which
resembles a DVI connector, and then to IC3304 for decoding into analog RGB. The
RGB signals are applied to pins 1, 3, and 13 of the selector IC, IC3309. The selected
RGB signals are output via pins 4, 14, and 15. The signals are then amplified by IC3310
and output to the J-Board via pins A30, A32, and A38 of the connector CN3303/J1.
Serial clock and data from the receiver box are applied via pins 6 and 7 of the video
connector CN3301 to the level shifter IC, IC3302. This IC reformats the DC and signal
levels of the clock and data pulses so that they match the specifications of IC3304 on
the DR-board. These pulses are then applied to IC3304.
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