Harman Kardon AVR247 Service Manual page 66

harman/kardon
AD0/CS 10
Address Bit 0 (I
is the chip select signal in SPI mode.
INT 11 Interrupt (Output ) - The CS42528 will generate an interrupt condition as per the Interrupt Mask register.
See "Interrupts" on page 40 for more details.
12 Reset ( Input ) - The device enters a low power mode and all internal registers are reset to their default
RST
settings when low.
13 Differential Right Channel Analog Input ( Input ) - Signals are presented differentially to the delta-sigma
AINR-
AINR+ 14 modulators via the AINR+/- pins.
15 Differential Left Channel Analog Input ( Input ) - Signals are presented differentially to the delta-sigma
AINL+
AINL- 16 modulators via the AINL+/- pins.
VQ 17 Quiescent Voltage ( Output ) - Filter connection for internal quiescent reference voltage.
FILT+ 18 Positive Voltage Reference ( Output ) - Positive reference voltage for the internal sampling circuits.
REFGND 19 Reference Ground ( Input ) - Ground reference for the internal sampling circuits.
AOUTA1 +,- 36,37 Differential Analog Output ( Output ) - The full-scale differential analog output level is specified in the
AOUTB1 +,- 35,34 Analog Characteristics specification table.
AOUTA2 +,- 32,33
AOUTB2 +,- 31,30
AOUTA3 +,- 28,29
AOUTB3 +,- 27,26
AOUTA4 +,- 22,23
AOUTB4 +,- 21,20
VA 24 Analog Power ( Input ) - Positive power supply for the analog section.
VARX 41
AGND 25 Analog Ground ( Input ) - Ground reference. Should be connected to analog ground.
40
MUTEC 38 Mute Control ( Output ) - The Mute Control pin outputs high impedance following an initial power-on con-
dition or whenever the PDN bit is set to a '1', forcing the codec into power-down mode. The signal will
remain in a high impedance state as long as the part is in power-down mode. The Mute Control pin goes
to the selected "active" state during reset, muting, or if the master clock to left/right clock frequency ratio
is incorrect. This pin is intended to be used as a control for external mute circuits to prevent the clicks
and pops that can occur in any single supply system. The use of external mute circuits are not manda-
tory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops.
LPFLT 39 PLL Loop Filter ( Output ) - An RC network should be connected between this pin and ground.
RXP7/GPO7 42 S/PDIF Receiver Input/ General Purpose Output ( Input/Output ) - Receiver inputs for S/PDIF encoded
RXP6/GPO6 43 data. The CS42528 has an internal 8:2 multiplexer to select the active receiver port, according to the
RXP5/GPO5 44 Receiver Mode Control 2 register. These pins can also be configured as general purpose output pins,
RXP4/GPO4 45 ADC Overflow indicators or Mute Control outputs according to the RXP/General Purpose Pin Control
46 registers.
RXP3/GPO3
47
RXP2/GPO2
RXP1/GPO1 48
49 S/PDIF Receiver Input ( Input ) - Dedicated receiver input for S/PDIF encoded data.
RXP0
TXP 50 S/PDIF Transmitter Output ( Output ) - S/PDIF encoded data output, mapped directly from one of the
receiver inputs as indicated by the Receiver Mode Control 2 register.
VLS 53 Serial Port Interface Power ( Input ) - Determines the required signal level for the serial port interfaces.
SAI_SDOUT 54 Serial Audio Interface Serial Data Output ( Output ) - Output for two's complement serial audio PCM
data from the S/PDIF incoming stream. This pin can also be configured to transmit the output of the inter-
nal and external ADCs.
RMCK 55 Recovered Master Clock ( Output ) - Recovered master clock output from the External Clock Reference
(OMCK, pin 59) or the PLL which is locked to the incoming S/PDIF stream or CX_LRCK.
18
2
C)/Control Port Chip Select (SPI) (Input ) - AD0 is a chip address pin in I
AVR247/230 Service Manual
CS42528
2
C mode; CS
DS586PP5
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