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3 7 63 1515 0
Pin No.
Pin Name
78
CLK_SEL [1]
79
CLK_SEL [2]
80
VSS
81
RESERVED
82
VDD3
83, 84
RESERVED
85
AGND_PLL
86
DA_XCK (16.934MHz)
87
AVDD_PLL
88
PGIO4
89
PGIO5
90
PGIO6
91
PGIO0
92
PGIO8
93
PGIO2/VSYNC/CSYNC
94
AVDD_PLL
95
NC
96, 97
NC
98
AGND PLL
99
VSS
100
NC
101
PGIO3/HSYNC
102
VDD3
103
PGIO1/VCK-OUT
TE
L 13942296513
104
VSS
105
GCK
106
VCK_IN (27MHz)
107
DA-EMP
108
DA-LRCK
109
VDDMAX_OUT
110
DA-DATA
111
DA-BCK
112
HD-OUT
113
HRDY
114
HINT
115
CDG-SCK
116
VSS
117
HCK
118
VDD3
119
HD-IN
120
VDD3
121
HSEL
122
CDG-SDATA
123
CDG-VFSY
124
CDG-SOS1
125 – 128
NC
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I/O
I
Clock select 1 input (Fixed at "H" in this set)
I
Clock select 2 input (Fixed at "H" in this set)
—
Ground
I
Clock select 3 input (Fixed at "L" in this set)
—
Power supply pin (+3.3 V)
O
Clock select 4 output (Fixed at "L" in this set)
—
Ground (for PLL system)
I
Main reference clock signal (16.9344 MHz=384 fs) from CXD3037R (IC601).
—
Power supply pin (+3.3 V) (for PLL system)
I/O
Not used in this set. (Open)
I/O
Not used in this set. (Open)
I/O
Not used in this set. (Open)
I/O
Not used in this set. (Open)
I/O
Not used in this set. (Open)
O
Vertical synchronized signal output (Not used in this set)
—
Power supply pin (+3.3 V) (for PLL system)
—
Not used. (Fixed at "L" in this set)
—
Not used. (Open)
—
Ground (for PLL system)
—
Ground
—
Not used. (Open)
I/O
Not used in this set. (Open)
—
Power supply pin (+3.3 V)
I/O
Not used in this set. (Open)
—
Ground
I
Connect to VSS in this set.
I
Main clock for video signal processor input from Buffer (27 MHz) (IC705).
O
Not used. (Open)
O
Digital audio L/R sampling clock signal (44.1 kHz) output to CXD3037R (IC601).
O
Fix the maximum output voltage (+5 V) certain output
O
Digital audio data output to CXD3037R (IC601).
O
Digital audio bit clock signal (2.8224 MHz) output to CXD3037R (IC601).
O
Serial data output to TMP87CM41U (IC803).
O
Ready signal output to TMP87CM41U (IC803)
O
Interrupt request signal output to TMP87CM41U (IC803).
I/O
CD graphics serial clock input/output (Fixed at "L" in this set)
—
Ground
I
Serial data transfer clock signal input from TMP87CM41U (IC803).
—
Power supply pin (+3.3 V)
I
Serial data input from TMP87CM41U (IC803).
—
Power supply pin (+3.3 V)
I
Command selection signal input from TMP87CM41U (IC803).
I
CD graphics serial data input (Fixed at "L" in this set)
I
CD graphics VFSY input (Fixed at "L" in this set)
I
CD graphics SOS1 input (Fixed at "L" in this set)
—
Not used. (Open)
x
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2 9
8
Pin Description
Q Q
3
6 7
1 3
1 5
co
.
9 4
2 8
0 5
8
2 9
9 4
2 8
m
9 9
9 9
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