Sony HDR-HC9 Service Manual page 40

3-2. OVERALL BLOCK DIAGRAM (2/7)
VC-500 BOARD (2/7)
RYI0_DE0 - RYI3_DE3
DV PB
RCI0_DE4 - RCI3_DE7
HYI_PLL27IN, HCI_FYI0
ADATAOUT0, ADATAOUT1
RYO0_EDHD - RYO3_SGOUT
DV REC
RCO0_EDHD - RCO3_FRMREF
HYO_SLGATE, HCO_FYI1
IC2101
(2/5)
BASE BAND
FS_EDGE_REF
SIGNAL
L24
PROCESSOR FRAT_REFO
N22
(8/24)
THYRQ_FVDI
F10
THCRQ_FHDI
C10
TFS_FCO
A3
MFLG_QRST
N7
FLAT_SYNC_FYO0
B9
VLAT_SYNC_FCI
A9
VLAT_IN_FYO1
F9
IC_2201_YO0 - IC_2201_YO7
HDV REC/PB, HDV-i.LINK
IC_2201_CO0 - IC_2201_CO7
TRN_HD, TRN_VD, TRN_FLD
TRN_VF_SYNC
B24
CKTRNO
D23
CKTRNI
B21
ADATAIN0, ADATAIN1
AUIN21, AUIN22
L1
CK27MFO1
K1
CKFSO
P25
CK64FSO
M25
MCLK
Y16
IC_2101_PCRERR
F8
IC_2101_SRCH
D9
IC_2101_FLD27MF
G9
WR01_SIM,
RDX_SIM
FRRV, TRRV, DRP
DXXA08_SIM, DXXA09_SIM
D24A00_SIM - D31A07_SIM
ALE_SIM
Y15
SD_OSD_VD
AC14
VREF
AE15
IC_2101_OEREF
AB16
XCS_IC_2101_SIM
AC15
XRST_VTR
D17
HDR-HC9/HC9E_L2
( ) : Number in parenthesis ( ) indicates the division number of schematic diagram where the component is located.
RYI0_DE0 - RYI3_DE3
DV PB
RCI0_DE4 - RCI3_DE7
HYI_PLL27IN, HCI_FYI0
ADATAOUT0, ADATAOUT1
RYO0_EDHD - RYO3_SGOUT
DV REC
RCO0_EDHD - RCO3_FRMREF
HYO_SLGATE, HCO_FYI1
ADATAIN0, ADATAIN1
FS_EDGE_REF
FRAT_REFO
THYRQ_FVDI
THCRQ_FHDI
TFS_FCO
MFLG_QRST
FLAT_SYNC_FYO0
VLAT_SYNC_FCI
VLAT_IN_FYO1
CK64FSO
CKFSO
CK27MFO1
HDV REC/PB, HDV-i.LINK
EBS[0] - EBS[7]
KCLK
AD12
ERDY
AD16
ERE
AD17
IC2201 AUDAI, AUENI
E18
HDV-MPEG VIDEO
ENCODER/DECODER,
F24
MPEG AUDIO AUDAO, AUENO
A22
SIGNAL PROCESSOR
(9/24)
AD18
BMDT16 - BMDT47
OMAD00 - OMAD12,
OMADB0, OMADB1
A20
P21
OMCEX
M24 J1 H7
OMCKE
IC2401
P24
L2 G1
OMCLK
256M
L1 G2
DDR-SDRAM
OMCLKX
K1 G3 IC_2101_PCRERR
(10/24)
OMDQ2
AC6 K8
IC_2101_SRCH
OMDQ3
Y1 K2 IC_2101_FLD27MF
OMDQ4
H4 F8
OMDQ5
A3 F2
OMDQS0
AC3 L8
OMDQS1
Y2 L2
OMCSX
K2 G8
OMWEX
J2 G7
OMRSX
J4 G9
BMDQS2
E1 E8
BMDQS3
B2 E2
D24A00_SIM - D31A07_SIM
ALE_SIM
N24
XCS_IC_2201
M20
XRST_IC_2201
D16
INT_IC_2201
P20
HDV PB, DV PB
R1
HDV REC, DV REC
W6
W1
IC2701
HDV STREAM
PROCESSOR,
MUX/DEMUX,
DV SIGNAL
PROCESSOR
C1 (11/24)
D2
A8
HDV-i.LINK,
F9 DV-i.LINK
C10 PD00 - PD07
A3
F6
F3
PCLK0
T25 L8
F2
E12 B8
M3
IDIR0
T23 M8 E2
IC3401
L1
XPEN0
R20 L9 J6
F1 HDV/DV
XIACC0
P20 M9 i.LINK D7
M1
FCLR0 INTERFACE
U21 J8
(16/24)
FR1
R25 J9
C1
X3401
24.576 MHz
C2
A20
F16
WR01_SIM,
F19
RDX_SIM TRRT
D12
C25
D23
D25
F23
F24
G23
J3
H24
A23
H23
FRRV, TRRT,
TRRV, DRP
DXXA00_SIM - DXXA10_SIM
C5
B3
D24A00_SIM - D31A07_SIM
G3
3-2
A : VIDEO SIGNAL
A : AUDIO SIGNAL
A : VIDEO/AUDIO SIGNAL
A
: VIDEO/AUDIO/SERVO SIGNAL
RFIN
RECDT
OVERALL (4/7)
6
RECCK (PAGE 3-4)
RECA1, RECA2
HDV-i.LINK, DV-i.LINK
OVERALL (6/7)
7
TPA+, TPA-, TPB+, TPB-
(PAGE 3-6)
SOL_PLL_ON
XCS_SOL
XRST_LINK
XRST_PHY
PWD, CNA, LPS, OFR2
SWP
ATF_LATCH
SCWIN
XCS_IC_2701_HD
XCS_IC_2701_DV
XRST_IC_2701_DV
XRST_IC_2701_1
XRST_IC_2701_2
FRRV, TRRT, TRRV, DRP
DXXA00_SIM - DXXA10_SIM
D24A00_SIM - D31A07_SIM
OVERALL (4/7)
8
(PAGE 3-4)
ALE_SIM
XCS_IC_2201
XRST_IC_2201
INT_IC_2201
MCLK
WR01_SIM, RDX_SIM
SD_OSD_VD
VREF
IC_2101_OEREF
XCS_IC_2101_SIM
XRST_VTR
CKFSO
OVERALL (3/7)
9
CK64FSO
(PAGE 3-3)