Operation Timing With Automatic Data Transmit/Receive Function Performed By Internal Clock; Interval Timing Through Cpu Processing (When The Internal Clock Is Operating) - NEC PD78052 User Manual

(a) When the automatic transmit/receive function is used by the internal clock
If bit 1 (CSIM11) of serial operation mode register 1 (CSIM1) is set at (1), the internal clock operates.
If the auto send and receive function is operated by the internal clock, interval timing by CPU processing
is as follows.
When bit 7 (ADTI7) of automatic data transmit/receive interval specify register (ADTI) is set to 0, the
interval depends on the CPU processing. When ADTI7 is set to 1, it depends on the contents of the ADTI
or CPU processing, whichever is greater.
Refer to Figure 18-5, "Automatic Data Transmit/Receive Interval Specify Register Format" for the intervals
which are set by the ADTI.
Table 18-2. Interval Timing Through CPU Processing (when the internal clock is operating)
When using multiplication instruction
When using division instruction
External access 1 wait mode
Other than above
Remark T
SCK
f
SCK
T
CPU
f
CPU
MAX. (a, b) : a or b, whichever is greater
Figure 18-24. Operation Timing with Automatic Data Transmit/Receive Function Performed by
Internal Clock
f
X
T
CPU
f
CPU
T
SCK
SCK1
SO1 D7
SI1 D7
f : Main system clock oscillation frequency
X
f : CPU clock (set by bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC) and
CPU
bit 0 (MCS) of the oscillation mode select register (OSMS).
T : 1/f
CPU CPU
T : 1/f
SCK SCK
f : Serial clock frequency
SCK
436
CHAPTER 18 SERIAL INTERFACE CHANNEL 1
CPU Processing
: 1/f
SCK
: Serial clock frequency
: 1/f
CPU
: CPU clock (set by bits 0 to 2 (PCC0 to PCC2) of the processor clock control
register (PCC) and bit 0 (MCS) of the oscillation mode selection register (OSMS))
D6 D5 D4
D6 D5 D4
Interval Time
Max. (2.5T , 13T
SCK CPU
Max. (2.5T , 20T
SCK CPU
Max. (2.5T , 9T
SCK CPU
Max. (2.5T , 7T
SCK CPU
D3 D2 D1
D3 D2 D1
)
)
)
)
Interval
D0
D0