Chapter 3 Features Of The Architecture And Memory Map - NEC PD750004 User Manual

Hardware name (symbol)
Address
b3
FD0H Clock output mode register (CLOM)
FDCH
Pull-up resistor specification register group A
(POGA)
FDEH
Pull-up resistor specification register group B
(POGB)
FE0H
Serial operation mode register (CSIM)
CSIE
CMDD RELD
FE2H
SBI control register (SBIC)
BSYE ACKD
FE4H
Serial I/O shift register (SIO)
FE6H
Slave address register (SVA)
PM33 PM32
FE8H
Port mode register group A (PMGA)
PM63 PM62
– PM2
FECH
Port mode register group B (PMGB)
PM7
–
FEEH
Port mode register group C (PMGC)
–
Note Whether a bit can be read or written depends on the bit.

CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP

Figure 3-7. µPD750008 I/O Map (4/5)
b2 b1 b0
COI WUP
CMDT RELT
ACKE ACKT
PM31 PM30
PM61 PM60
– –
– PM5 PM4
– – PM8
– – –
Number of bits that can be
manipulated
R/ W
1 bit 4 bits
R/W –
R/W – –
R/W – –
– –
R/ W
–
(R) (W)
R/ W –
R/ W – –
–
R/W –
R/W
– –
R/W – –
R/W – –
Bit
manipulation
addressing
8 bits
– –
–
–
–
mem.bit
Whether this
location is read-
or write-
– mem.bit
accessible de-
pends on the bit.
–
–
–
–
–
Remarks
Note
4 3