Pin Function - Denon AVR-2309CI Service Manual

Pin Function

QQ
3 7 63 1515 0
Symbol
A0-A10
BA0, BA1
C A S
CKE
CLK
C S
I/O0 to 2, 4, 5, 7, 8, 10,11,13
I/O31 74,76,77,79,80,82,83,85
45,47,48,50,51,53,54,56
31,33,34,36,37,39,40,42
DQM0 16,28,59,71
DQM3
TE
L 13942296513
R A S
W E
V 3,9,35,41,49,55,25,81
CCQ
V 1,15,29,43
CC
GND 6,12,32,38,46,52,78,84
Q
GND 44,58,72,86
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Pin No. Type Function (In Detail)
25 to 27 Input Pin Address Inputs: A0-A10 are sampled during the ACTIVE
60 to 66 command (row-address A0-A10) and READ/WRITE command (A0-A7
24 with A10 defining auto precharge) to select one location out of the memory array
in the respective bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
22,23 Input Pin Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied.
18 Input Pin C AS , in conjunction with the R AS and WE , forms the device command. See the
"Command Truth Table" for details on device commands.
67 Input Pin The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When
CKE is LOW, the device will be in either power-down mode, clock suspend mode,
or self refresh mode. CKE is an asynchronous input.
68 Input Pin CLK is the master clock input for this device. Except for CKE, all inputs to this
device are acquired in synchronization with the rising edge of this pin.
20 Input Pin The C S input determines whether command input is enabled within the device.
Command input is enabled when C S is LOW, and disabled with C S is HIGH. The
device remains in the previous state when C S is HIGH.
I/O Pin I/O0 to I/O15 are I/O pins. I/O through these pins can be controlled in byte units
using the DQM0-DQM3 pins
Input Pin DQMx control thel ower and upper bytes of the I/O buffers. In read mode,
the output buffers are place in a High-Z state. During a WRITE cycle the input data
is masked. When DQMx is sampled HIGH and is an input mask signal for write
accesses and an output enable signal for read accesses. I/O0 through I/O7 are
controlled by DQM0. I/O8 throughI/O15 are controlled by DQM1. I/O16 through I/
O23 are controlled by DQM2. I/O24 through I/O31 are controlled by DQM3.
19 Input Pin R AS , in conjunction with C AS and WE , forms the device command. See the
"Command Truth Table" item for details on device commands.
17 Input Pin WE , in conjunction with R AS and C AS , forms the device command. See the
"Command Truth Table" item for details on device commands.
Supply Pin V
CCQ
Supply Pin V
CC
Supply Pin GND
Supply Pin GND is the device internal ground.
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8
Q Q
3 6 7 1 3
is the output buffer power supply.
is the device internal power supply.
is the output buffer ground.
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