Post Codes - Acer Aspire 5755 Service Manual

Post Codes

The following are the InsydeH2O™ Functionality POST code tables. The components of the
POST code table includes: SEC phase, PEI phase, DXE phase, BDS phase, CSM functions,
S3 functions and ACPI functions.
Table 4-2. POST Code Range
SEC
PEI
DXE
BDS
SMM
S3
ASL
PostBDS
InsydeH2ODDT™ Reserve
OEM Reserve
Reserved
Table 4-3. SEC Phase POST Code Table
(Include\PostCode.h)
SEC_SYSTEM_POWER_ON
SEC_BEFORE_MICROCODE_PATCH
SEC_AFTER_MICROCODE_PATCH
SEC_ACCESS_CSR*
SEC_GENERIC_MSRINIT*
SEC_CPU_SPEEDCFG*
SEC_SETUP_CAR_OK
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Phase
0x01 - 0x0F
0x70 - 0x9F
0x40 - 0x6F
0x10 - 0x3F
0xA0 - 0xBF
0xC0 - 0xCF
0x51 – 0x55
0xE1 – 0xE4
0xF9 – 0xFE
0xD0 – 0xD7
0xE8 – 0xEB
0xD8 – 0xE0
0xE5 – 0xE7
0xEC – 0xF8
Functionality Name
POST Code Range
Phase Post
Code
SEC 01
SEC 02
SEC 03
SEC 04
SEC 05
SEC 06
SEC 07
Description
CPU power on and switch to
Protected mode
Patching CPU microcode
Setup Cache as RAM
PCIE MMIO Base Address
initial
CPU Generic MSR
initialization
Setup CPU speed
Cache as RAM test
0
4-25